/*!
    \file    change log.txt
    \brief   change log for GD32F527 firmware

    \version 2026-01-31, V1.4.0, firmware for GD32F527
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.4.0 2026-01-31 ******************************************************************************************
______________________COMMON_______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/CMSIS/GD/GD32F527/Source/GCC
../GD32F527_Firmware_Library/Template/GD32EBuilder_project

fix reason:
GD32EmbeddedBuilder development environment added

V1.3.0:
None 
V1.4.0:
New added.

______________________CAU&PKCAU&RTC&SAI&TRNG&DAC&CAN&TIMER_________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_cau_aes.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_cau_des.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_cau_tdes.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_pkcau.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rtc.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_sai.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_trng.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_dac.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_can.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_timer.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_dma.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_i2c.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_i2c_add.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_fwdgt.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_wwdgt.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_exti.c

fix reason:
Fixed MISRA error：A function shall have a single point of exit at the end of the function.

______________________ADC ______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/ADC/ADC0_temperature_Vref_Vbat/readme.txt

fix reason:
Update the readme.txt for ADC example

V1.3.0:
  As the AD convertion begins by software. We can watch temperature, vref_value and
vbat_value in debug mode or by COM.

V1.4.0:
 As the AD convertion begins by software. We can watch temperature, vref_value and
vbat_value in debug mode or by COM.
  This example requires printing floating-point data. Please configure the "Settings->GD ARM MCU Linker->Miscellaneous"
 option in the Embedded Builder project and check "Use float with nano printf" to enable this functionality.

______________________IPA______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/IPA/IPA_2images_blend/logo.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_2images_blend/logo2.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_image_copy/logo.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_image_copy/image_copy.h
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_ipa.h
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_ipa.c

fix reason:
1. Add 4-byte alignment
2. Add configuration for address of IPA

V1.3.0:
../GD32F527_Firmware_Library/Examples/IPA/IPA_2images_blend/logo.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_image_copy/logo.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_2images_blend/logo2.h

const unsigned char gImage_logo2[73280] = { /* 0X00,0X10,0XE5,0X00,0XA0,0X00,0X01,0X1B, */
../GD32F527_Firmware_Library/Examples/IPA/IPA_image_copy/image_copy.h
const unsigned char gImage_image_copy[211200] = { /* 0X00,0X10,0XE0,0X01,0XDC,0X00,0X01,0X1B, */

V1.4.0:

../GD32F527_Firmware_Library/Examples/IPA/IPA_2images_blend/logo.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_image_copy/logo.h
../GD32F527_Firmware_Library/Examples/IPA/IPA_2images_blend/logo2.h
#if defined(__GNUC__)
    __attribute__((aligned(4))) const unsigned char gImage_logo[73280] = { /* 0X00,0X10,0XE5,0X00,0XA0,0X00,0X01,0X1B, */
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
    __align(4) const unsigned char gImage_logo[73280] = { /* 0X00,0X10,0XE5,0X00,0XA0,0X00,0X01,0X1B, */
#elif defined(__ICCARM__)
    #pragma data_alignment=4
    const unsigned char gImage_logo[73280] = { /* 0X00,0X10,0XE5,0X00,0XA0,0X00,0X01,0X1B, */
#else
    const unsigned char gImage_logo[73280] = { /* 0X00,0X10,0XE5,0X00,0XA0,0X00,0X01,0X1B, */
#endif

../GD32F527_Firmware_Library/Examples/IPA/IPA_image_copy/image_copy.h
#if defined(__GNUC__)
    __attribute__((aligned(4))) const unsigned char gImage_image_copy[211200] = { /* 0X00,0X10,0XE0,0X01,0XDC,0X00,0X01,0X1B, */
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
    __align(4) const unsigned char gImage_image_copy[211200] = { /* 0X00,0X10,0XE0,0X01,0XDC,0X00,0X01,0X1B, */
#elif defined(__ICCARM__)
    #pragma data_alignment=4
    const unsigned char gImage_image_copy[211200] = { /* 0X00,0X10,0XE0,0X01,0XDC,0X00,0X01,0X1B, */
#else
    const unsigned char gImage_image_copy[211200] = { /* 0X00,0X10,0XE0,0X01,0XDC,0X00,0X01,0X1B, */
#endif

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_ipa.h
/* configure foreground memory base address */
void ipa_foreground_memaddr_config(uint32_t address);
/* configure background memory base address */
void ipa_background_memaddr_config(uint32_t address);
/* configure destination memory base address */
void ipa_destination_memaddr_config(uint32_t address);
/* configure foreground LUT memory base address */
void ipa_foreground_lut_memaddr_config(uint32_t address);
/* configure background LUT memory base address */
void ipa_background_lut_memaddr_config(uint32_t address);

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_ipa.c
/*!
    \brief    configure foreground memory base address
    \param[in]  address: memory base address
    \param[out] none
    \retval     none
*/
void ipa_foreground_memaddr_config(uint32_t address)
{
    IPA_FMADDR = address;
}

/*!
    \brief    configure background memory base address
    \param[in]  address: memory base address
    \param[out] none
    \retval     none
*/
void ipa_background_memaddr_config(uint32_t address)
{
    IPA_BMADDR = address;
}

/*!
    \brief    configure destination memory base address
    \param[in]  address: memory base address
    \param[out] none
    \retval     none
*/
void ipa_destination_memaddr_config(uint32_t address)
{
    IPA_DMADDR = address;
}

/*!
    \brief    configure foreground LUT memory base address
    \param[in]  address: memory base address
    \param[out] none
    \retval     none
*/
void ipa_foreground_lut_memaddr_config(uint32_t address)
{
    IPA_FLMADDR = address;
}

/*!
    \brief    configure background LUT memory base address
    \param[in]  address: memory base address
    \param[out] none
    \retval     none
*/
void ipa_background_lut_memaddr_config(uint32_t address)
{
    IPA_BLMADDR = address;
}

______________________TLI______________________________________________________________________________________________
fix reason:
Add configuration for address of TLI

V1.3.0:

V1.4.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_tli.h
/* configure the TLI layer frame buffer address */
void tli_layer_frame_bufaddr_config(uint32_t layerx, uint32_t address);

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_tli.c
/*!
    \brief    configure the TLI layer frame buffer address
    \param[in]  layerx: LAYERx(x=0,1)
    \param[in]  address: frame buffer address
    \param[out] none
    \retval     none
*/
void tli_layer_frame_bufaddr_config(uint32_t layerx, uint32_t address)
{
    TLI_LxFBADDR(layerx) = address;
}

______________________TIMER______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/TIMER/TIMERs_cascadesynchro/main.c

fix reason:
Example TIMERs_cascadesynchro update
V1.3.0:
void gpio_config(void)
{
    ...
    /*configure PA6(TIMER2 CH0) as alternate function*/
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
    gpio_af_set(GPIOA, GPIO_AF_2, GPIO_PIN_6);
    ...
}
V1.4.0:
void gpio_config(void)
{
    ...
    /*configure PB4(TIMER2 CH0) as alternate function*/
    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4);
    gpio_af_set(GPIOB, GPIO_AF_2, GPIO_PIN_4);
    ...
}
______________________CAN______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_can.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_can.h
../GD32F527_Firmware_Library/Examples/CAN/communication_FDmode/main.c

fix reason:
1. Determine whether the CAN controller has three mailboxes transmitting simultaneously, and whether the mailbox to be aborted is the last one. 
   If such an operation is performed, the code will exit and notify the customer that the abort operation has failed.
2. CAN FD demo Transmission delay compensation modify.
3. CAN filter base address modify.
V1.3.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_can.h
#define CAN_F23DATA0(canx)                 REG32((canx) + 0x000003F8U)        /*!< CAN filter 23 data 0 register */

#define CAN_F17DATA1(canx)                 REG32((canx) + 0x0000024CU)        /*!< CAN filter 17 data 1 register */

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_can.c
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
{
    if(CAN_MAILBOX0 == mailbox_number) {
        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
        while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) {
        }
    } else if(CAN_MAILBOX1 == mailbox_number) {
        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
        while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) {
        }
    } else if(CAN_MAILBOX2 == mailbox_number) {
        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
        while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) {
        }
    } else {
        /* illegal parameters */
    }
}
../GD32F527_Firmware_Library/Examples/CAN/communication_FDmode/main.c
    can_fd_parameter.delay_compensation = ENABLE;
    can_fd_tdc_parameter.tdc_filter = 0x04;
    can_fd_tdc_parameter.tdc_mode = CAN_TDCMOD_CALC_AND_OFFSET;
    can_fd_tdc_parameter.tdc_offset = 0x04;
V1.4.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_can.c
ErrStatus can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
{
    ErrStatus reval = SUCCESS;
    /* timeout for CAN_TSTAT_MSTx bits */
    uint32_t timeout = CAN_TIMEOUT;
    uint32_t reg_value0 = 0U;
    uint32_t reg_value1 = 0U;

    /* get the status of transmit FIFO order */
    reg_value0 = CAN_CTL(can_periph) & CAN_CTL_TFO;

    if(CAN_MAILBOX0 == mailbox_number) {
        reg_value1 = CAN_TSTAT(can_periph) & (CAN_TSTAT_TMLS0 | CAN_ALL_MAILBOX_EMPTY);
        if((CAN_CTL_TFO == reg_value0) && (CAN_TSTAT_TMLS0 == reg_value1)){
            reval = ERROR;
        } else {
            CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
            while((CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) && (0U != timeout)) {
                timeout--;
            }
            if(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){
                reval = ERROR;
            }
        }
    } else if(CAN_MAILBOX1 == mailbox_number) {
        reg_value1 = CAN_TSTAT(can_periph) & (CAN_TSTAT_TMLS1 | CAN_ALL_MAILBOX_EMPTY);
        if((CAN_CTL_TFO == reg_value0) && (CAN_TSTAT_TMLS1 == reg_value1)){
            reval = ERROR;
        }else{
            CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
            while((CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) && (0U != timeout)) {
                timeout--;
            }
            if(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){
                reval = ERROR;
            }
        }
        
    } else if(CAN_MAILBOX2 == mailbox_number) {
        reg_value1 = CAN_TSTAT(can_periph) & (CAN_TSTAT_TMLS2 | CAN_ALL_MAILBOX_EMPTY);
        if((CAN_CTL_TFO == reg_value0) && (CAN_TSTAT_TMLS2 == reg_value1)){
            reval = ERROR;
        }else{
            CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
            while((CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) && (0U != timeout)) {
                timeout--;
            }
            if(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){
                reval = ERROR;
            }
        }
    } else {
        /* illegal parameters */
    }
    return reval;
}

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_can.h
/* CAN mailbox empty status mask */
#define CAN_ALL_MAILBOX_EMPTY              ((uint32_t)0x1C000000U)      /*!< CAN mailbox empty status mask */

#define CAN_F23DATA0(canx)                 REG32((canx) + 0x000002F8U)        /*!< CAN filter 23 data 0 register */

#define CAN_F17DATA1(canx)                 REG32((canx) + 0x000002CCU)        /*!< CAN filter 17 data 1 register */

../GD32F527_Firmware_Library/Examples/CAN/communication_FDmode/main.c
    can_fd_parameter.delay_compensation = DISABLE;
    can_fd_tdc_parameter.tdc_filter = 0x04;
    can_fd_tdc_parameter.tdc_mode = CAN_TDCMOD_CALC_AND_OFFSET;
    can_fd_tdc_parameter.tdc_offset = 0x14;
	
../GD32F527_Firmware_Library/Examples/ENET/Telnet/lwip-2.1.2

______________________ENET______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/ENET/Telnet

fix reason:
upgrade lwip version from to 2.2.1

______________________FWDGT______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/FWDGT/FWDGT_key/main.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_fwdgt.h

fix reason:
First enable the FWDGT, then write PSC and RLD, and wait for RUD and PUD to clear.

V1.3.0:
../GD32F527_Firmware_Library/Examples/FWDGT/FWDGT_key/main.c
    /* confiure FWDGT counter clock: 32KHz(IRC32K) / 64 = 0.5 KHz */
    fwdgt_config(2 * 500, FWDGT_PSC_DIV64);

    /* After 2 seconds to generate a reset */
    fwdgt_enable();

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_fwdgt.h
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);

V1.4.0:
../GD32F527_Firmware_Library/Examples/FWDGT/FWDGT_key/main.c
    /* confiure FWDGT counter clock: 32KHz(IRC32K) / 64 = 0.5 KHz */
    fwdgt_config(2 * 500, FWDGT_PSC_DIV64);

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_fwdgt.h
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value);

______________________MISC______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_misc.h
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_misc.c
../GD32F527_Firmware_Library/Examples/CORTEX_M

fix reason:
1. modify MPU_ACCESS_OUTER_SHAREABLE micro from 1 to 2
2. add default priority group set in the irq enable function
3. add MPU function in the misc file, and update nvic_irq_enable implement
V1.3.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_misc.h
#define MPU_ACCESS_OUTER_SHAREABLE             ((uint8_t)0x01U)        /*!< MPU region outer shareable */

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_misc.c
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t nvic_prigroup, nvic_priority;
...
}


void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
    /* use the priority group value to get the temp_pre and the temp_sub */
    if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) {
        temp_pre = 0x0U;
        temp_sub = 0x4U;
    } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) {
        temp_pre = 0x1U;
        temp_sub = 0x3U;
    } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) {
        temp_pre = 0x2U;
        temp_sub = 0x2U;
    } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) {
        temp_pre = 0x3U;
        temp_sub = 0x1U;
    } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) {
        temp_pre = 0x4U;
        temp_sub = 0x0U;
    } else {
        nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
        temp_pre = 0x2U;
        temp_sub = 0x2U;
    }
    /* get the temp_priority to fill the NVIC->IP register */
    temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
    temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
    temp_priority = temp_priority << 0x04U;
    NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
    /* enable the selected IRQ */
    NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
}

void nvic_irq_disable(IRQn_Type nvic_irq)
{
    /* disable the selected IRQ.*/
    NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
}

V1.4.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_misc.h
#define MPU_ACCESS_OUTER_SHAREABLE             ((uint8_t)0x02U)        /*!< MPU region outer shareable */

#if (__MPU_PRESENT == 1U)

#define MPU_REGION_NUMBER0                     ((uint8_t)0x00U)        /*!< MPU region number 0 */
#define MPU_REGION_NUMBER1                     ((uint8_t)0x01U)        /*!< MPU region number 1 */
#define MPU_REGION_NUMBER2                     ((uint8_t)0x02U)        /*!< MPU region number 2 */
#define MPU_REGION_NUMBER3                     ((uint8_t)0x03U)        /*!< MPU region number 3 */
#define MPU_REGION_NUMBER4                     ((uint8_t)0x04U)        /*!< MPU region number 4 */
#define MPU_REGION_NUMBER5                     ((uint8_t)0x05U)        /*!< MPU region number 5 */
#define MPU_REGION_NUMBER6                     ((uint8_t)0x06U)        /*!< MPU region number 6 */
#define MPU_REGION_NUMBER7                     ((uint8_t)0x07U)        /*!< MPU region number 7 */

#define MPU_REGION_PRIVILEGED_RW               ((uint8_t)0x00U)        /*!< MPU region read/write by privileged code only */
#define MPU_REGION_ALL_RW                      ((uint8_t)0x01U)        /*!< MPU region read/write by any privilege level  */
#define MPU_REGION_PRIVILEGED_RO               ((uint8_t)0x02U)        /*!< MPU region read-only by privileged code only  */
#define MPU_REGION_ALL_RO                      ((uint8_t)0x03U)        /*!< MPU region read-only by any privilege level   */

#define MPU_ACCESS_NOT_SHAREABLE               ((uint8_t)0x00U)        /*!< MPU access shareable */
#define MPU_ACCESS_OUTER_SHAREABLE             ((uint8_t)0x01U)        /*!< MPU region outer shareable */
#define MPU_ACCESS_INNER_SHAREABLE             ((uint8_t)0x03U)        /*!< MPU region inner shareable */

#define MPU_INSTRUCTION_EXEC_PERMIT            ((uint8_t)0x00U)        /*!< execution of an instruction fetched from this region permitted */
#define MPU_INSTRUCTION_EXEC_NOT_PERMIT        ((uint8_t)0x01U)        /*!< execution of an instruction fetched from this region not permitted */

#define MPU_MODE_HFNMI_PRIVDEF_NONE            ((uint32_t)0x00000000U) /*!< HFNMIENA and PRIVDEFENA are 0 */
#define MPU_MODE_HARDFAULT_NMI                 MPU_CTRL_HFNMIENA_Msk   /*!< use the MPU for memory accesses by HardFault and NMI handlers only */
#define MPU_MODE_PRIV_DEFAULT                  MPU_CTRL_PRIVDEFENA_Msk /*!< enables the default memory map as a background region for privileged access only */
#define MPU_MODE_HFNMI_PRIVDEF                 ((uint32_t)MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< HFNMIENA and PRIVDEFENA are 1 */

#define MPU_ATTRIBUTE_NUMBER0                  ((uint8_t)0x00U)        /*!< MPU attribute number 0 */
#define MPU_ATTRIBUTE_NUMBER1                  ((uint8_t)0x01U)        /*!< MPU attribute number 1 */
#define MPU_ATTRIBUTE_NUMBER2                  ((uint8_t)0x02U)        /*!< MPU attribute number 2 */
#define MPU_ATTRIBUTE_NUMBER3                  ((uint8_t)0x03U)        /*!< MPU attribute number 3 */
#define MPU_ATTRIBUTE_NUMBER4                  ((uint8_t)0x04U)        /*!< MPU attribute number 4 */
#define MPU_ATTRIBUTE_NUMBER5                  ((uint8_t)0x05U)        /*!< MPU attribute number 5 */
#define MPU_ATTRIBUTE_NUMBER6                  ((uint8_t)0x06U)        /*!< MPU attribute number 6 */
#define MPU_ATTRIBUTE_NUMBER7                  ((uint8_t)0x07U)        /*!< MPU attribute number 7 */

#define MPU_MEMORY_DEVICE                      ((uint8_t)0x00U)        /*!< MPU device memory */
#define MPU_MEMORY_NORMAL                      ((uint8_t)0x01U)        /*!< MPU normal memory */

#define MPU_DEVICE_nGnRnE                      ((uint8_t)0x00U)        /*!< device, nogather, noreorder, noearly acknowledge */
#define MPU_DEVICE_nGnRE                       ((uint8_t)0x04U)        /*!< device, nogather, noreorder, early acknowledge*/
#define MPU_DEVICE_nGRE                        ((uint8_t)0x08U)        /*!< device, nogather, reorder, early acknowledge */
#define MPU_DEVICE_GRE                         ((uint8_t)0x0CU)        /*!< device, gather, reorder, early acknowledge */

#define MPU_OUTER_DEVICE                       ((uint8_t)0x00U)        /*!< device memory */
#define MPU_NORMAL_OUTER_WT_TRAN_W_ALLOC       ((uint8_t)0x10U)        /*!< normal memory, outer write-through transient, write with allocate */
#define MPU_NORMAL_OUTER_WT_TRAN_R_ALLOC       ((uint8_t)0x20U)        /*!< normal memory, outer write-through transient, read with allocate */
#define MPU_NORMAL_OUTER_WT_TRAN_RW_ALLOC      ((uint8_t)0x30U)        /*!< normal memory, outer write-through transient, read and write with allocate */
#define MPU_NORMAL_OUTER_NON_CACHEABLE         ((uint8_t)0x40U)        /*!< normal memory, outer non-cacheable */
#define MPU_NORMAL_OUTER_WB_TRAN_W_ALLOC       ((uint8_t)0x50U)        /*!< normal memory, outer write-back transient, write with allocate */
#define MPU_NORMAL_OUTER_WB_TRAN_R_ALLOC       ((uint8_t)0x60U)        /*!< normal memory, outer write-back transient, read with allocate */
#define MPU_NORMAL_OUTER_WB_TRAN_RW_ALLOC      ((uint8_t)0x70U)        /*!< normal memory, outer write-back transient, read and write with allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_NO_ALLOC  ((uint8_t)0x80U)        /*!< normal memory, outer write-through non-transient, no allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_W_ALLOC   ((uint8_t)0x90U)        /*!< normal memory, outer write-back non-transient, write with allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_R_ALLOC   ((uint8_t)0xA0U)        /*!< normal memory, outer write-back non-transient, read with allocate */
#define MPU_NORMAL_OUTER_WT_NON_TRAN_RW_ALLOC  ((uint8_t)0xB0U)        /*!< normal memory, outer write-back non-transient, read and write with allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_NO_ALLOC  ((uint8_t)0xC0U)        /*!< normal memory, outer write-back non-transient, no allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_W_ALLOC   ((uint8_t)0xD0U)        /*!< normal memory, outer write-back non-transient, write with allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_R_ALLOC   ((uint8_t)0xE0U)        /*!< normal memory, outer write-back non-transient, read with allocate */
#define MPU_NORMAL_OUTER_WB_NON_TRAN_RW_ALLOC  ((uint8_t)0xF0U)        /*!< normal memory, outer write-back non-transient, read and write with allocate */

#define MPU_NORMAL_INNER_WT_TRAN_W_ALLOC       ((uint8_t)0x01U)        /*!< normal memory, inner write-through transient, write with allocate */
#define MPU_NORMAL_INNER_WT_TRAN_R_ALLOC       ((uint8_t)0x02U)        /*!< normal memory, inner write-through transient, read with allocate */
#define MPU_NORMAL_INNER_WT_TRAN_RW_ALLOC      ((uint8_t)0x03U)        /*!< normal memory, inner write-through transient, read and write with allocate */
#define MPU_NORMAL_INNER_NON_CACHEABLE         ((uint8_t)0x04U)        /*!< normal memory, inner non-cacheable */
#define MPU_NORMAL_INNER_WB_TRAN_W_ALLOC       ((uint8_t)0x05U)        /*!< normal memory, inner write-back transient, write with allocate */
#define MPU_NORMAL_INNER_WB_TRAN_R_ALLOC       ((uint8_t)0x06U)        /*!< normal memory, inner write-back transient, read with allocate */
#define MPU_NORMAL_INNER_WB_TRAN_RW_ALLOC      ((uint8_t)0x07U)        /*!< normal memory, inner write-back transient, read and write with allocate */
#define MPU_NORMAL_INNER_WT_NON_TRAN_NO_ALLOC  ((uint8_t)0x08U)        /*!< normal memory, inner write-through non-transient */
#define MPU_NORMAL_INNER_WT_NON_TRAN_W_ALLOC   ((uint8_t)0x09U)        /*!< normal memory, inner write-back non-transient, write with allocate */
#define MPU_NORMAL_INNER_WT_NON_TRAN_R_ALLOC   ((uint8_t)0x0AU)        /*!< normal memory, inner write-back non-transient, read with allocate */
#define MPU_NORMAL_INNER_WT_NON_TRAN_RW_ALLOC  ((uint8_t)0x0BU)        /*!< normal memory, inner write-back non-transient, read and write with allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_NO_ALLOC  ((uint8_t)0x0CU)        /*!< normal memory, inner write-back non-transient, no allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_W_ALLOC   ((uint8_t)0x0DU)        /*!< normal memory, inner write-back non-transient, write with allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_R_ALLOC   ((uint8_t)0x0EU)        /*!< normal memory, inner write-back non-transient, read with allocate */
#define MPU_NORMAL_INNER_WB_NON_TRAN_RW_ALLOC  ((uint8_t)0x0FU)        /*!< normal memory, inner write-back non-transient, read and write with allocate */

#endif /* __MPU_PRESENT */

#if (__MPU_PRESENT == 1U)

/* MPU region init parameter struct definitions */
typedef struct {
    uint8_t  region_number;           /*!< region number */
    uint32_t region_base_address;     /*!< region base address */
    uint32_t region_limit_address;    /*!< region limit address */
    uint8_t  access_permission;       /*!< access permissions(AP) field */
    uint8_t  instruction_exec;        /*!< execute never */
    uint8_t  shareability;            /*!< defines the shareability for Normal memory */
    uint8_t  attribute_index;         /*!< attribute index */
} mpu_region_init_struct;

typedef struct {
  uint8_t attribute_number;           /*!< attribute number */
  uint8_t memory_type;                /*!< memory type */
  uint8_t outer_attributes;           /*!< outer memory attributes */
  uint8_t inner_attributes;           /*!< inner memory attributes */
} mpu_attribute_init_struct;

#endif /* __MPU_PRESENT */

#if (__MPU_PRESENT == 1U)
/* enable the MPU */
void mpu_enable(uint32_t MPU_Control);
/* disable the MPU */
void mpu_disable(void);
/* initialize mpu_region_init_struct with the default values */
void mpu_region_struct_para_init(mpu_region_init_struct *region_init_struct);
/* initialize mpu_attribute_init_struct with the default values */
void mpu_attribute_struct_para_init(mpu_attribute_init_struct *attribute_init_struct);
/* configure the MPU region */
void mpu_region_config(mpu_region_init_struct *region_init_struct);
/* configure the MPU attribute */
void mpu_attribute_config(mpu_attribute_init_struct *attribute_init_struct);
/* enable the MPU region */
void mpu_region_enable(void);
#endif /* __MPU_PRESENT */

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_misc.c
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
{
    uint32_t nvic_prigroup, nvic_priority;

    /* check current priority group */
    switch(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) {
    case NVIC_PRIGROUP_PRE0_SUB4:
    case NVIC_PRIGROUP_PRE1_SUB3:
    case NVIC_PRIGROUP_PRE2_SUB2:
    case NVIC_PRIGROUP_PRE3_SUB1:
    case NVIC_PRIGROUP_PRE4_SUB0:
        break;
    default:
        nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
        break;
    }
    /* get the priority group value */
    nvic_prigroup = NVIC_GetPriorityGrouping();

    /* encoding the pre-emption, subpriority priority */
    nvic_priority = NVIC_EncodePriority(nvic_prigroup, (uint32_t)nvic_irq_pre_priority, (uint32_t)nvic_irq_sub_priority);
    /* set priority */
    NVIC_SetPriority(nvic_irq, nvic_priority);

    /* enable the selected IRQ */
    NVIC_EnableIRQ(nvic_irq);
}

void nvic_irq_disable(IRQn_Type nvic_irq)
{
    /* disable the selected IRQ */
    NVIC_DisableIRQ(nvic_irq);
}

#if (__MPU_PRESENT == 1U)

/*!
    \brief      enable the MPU
    \param[in]  MPU_Control: select a different MPU mode
      \arg        MPU_MODE_HFNMI_PRIVDEF_NONE: HFNMIENA and PRIVDEFENA are 0
      \arg        MPU_MODE_HARDFAULT_NMI: use the MPU for memory accesses by HardFault and NMI handlers only
      \arg        MPU_MODE_PRIV_DEFAULT: enables the default memory map as a background region for privileged access only
      \arg        MPU_MODE_HFNMI_PRIVDEF: HFNMIENA and PRIVDEFENA are 1
    \param[out] none
    \retval     none
*/
void mpu_enable(uint32_t MPU_Control)
{
    __DMB();
    /* enable the MPU */
    MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
    SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
    __DSB();
    __ISB();
}

/*!
    \brief      disable the MPU
    \param[in]  none
    \param[out] none
    \retval     none
*/
void mpu_disable(void)
{
    __DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
    SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
    /* disable the MPU */
    MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
    __DSB();
    __ISB();
}

/*!
    \brief      initialize mpu_region_init_struct with the default values
    \param[in]  region_init_struct: pointer to a mpu_region_init_struct structure
    \param[out] none
    \retval     none
*/
void mpu_region_struct_para_init(mpu_region_init_struct *region_init_struct)
{
    region_init_struct->region_number        = MPU_REGION_NUMBER0;
    region_init_struct->region_base_address  = 0x00000000U;
    region_init_struct->region_limit_address = 0x00000000U;
    region_init_struct->instruction_exec     = MPU_INSTRUCTION_EXEC_PERMIT;
    region_init_struct->access_permission    = MPU_REGION_PRIVILEGED_RW;
    region_init_struct->shareability         = MPU_ACCESS_NOT_SHAREABLE;
    region_init_struct->attribute_index      = MPU_ATTRIBUTE_NUMBER0;
}

/*!
    \brief      initialize mpu_attribute_init_struct with the default values
    \param[in]  attribute_init_struct: pointer to a mpu_attribute_init_struct structure
    \param[out] none
    \retval     none
*/
void mpu_attribute_struct_para_init(mpu_attribute_init_struct *attribute_init_struct)
{
    attribute_init_struct->attribute_number = MPU_ATTRIBUTE_NUMBER0;
    attribute_init_struct->memory_type      = MPU_MEMORY_DEVICE;
    attribute_init_struct->inner_attributes = MPU_DEVICE_nGnRnE;
    attribute_init_struct->outer_attributes = MPU_OUTER_DEVICE;
}

/*!
    \brief      configure the MPU region
    \param[in]  region_init_struct: MPU initialization structure
                  region_number: region number
                                 MPU_REGION_NUMBERn (n=0,..,7)
                  region_base_address: region base address
                  region_limit_address: region limit address
                  access_permission: MPU_REGION_PRIVILEGED_RW, MPU_REGION_ALL_RW, MPU_AP_PRIV_RW_UNPRIV_RO, MPU_REGION_ALL_RO
                  instruction_exec: MPU_INSTRUCTION_EXEC_PERMIT, MPU_INSTRUCTION_EXEC_NOT_PERMIT
                  shareability: MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_OUTER_SHAREABLE, MPU_ACCESS_INNER_SHAREABLE
                  attribute_index: attribute index
                                   MPU_ATTRIBUTE_NUMBERn (n=0,..,7)
    \param[out] none
    \retval     none
*/
void mpu_region_config(mpu_region_init_struct *region_init_struct)
{
    __DMB();
    /* select the Region number  */
    MPU->RNR = region_init_struct->region_number;
    /* disable the Region  */
    MPU->RLAR &= ~(MPU_RLAR_EN_Msk);
    MPU->RBAR = (((uint32_t)region_init_struct->region_base_address & 0xFFFFFFE0UL)   | 
                 ((uint32_t)region_init_struct->shareability << MPU_RBAR_SH_Pos)      |
                 ((uint32_t)region_init_struct->access_permission << MPU_RBAR_AP_Pos) |
                 ((uint32_t)region_init_struct->instruction_exec << MPU_RBAR_XN_Pos)) ;
    
    MPU->RLAR = (((uint32_t)region_init_struct->region_limit_address & 0xFFFFFFE0UL)      |
                 ((uint32_t)region_init_struct->attribute_index << MPU_RLAR_AttrIndx_Pos));
}

/*!
    \brief      configure the MPU attribute
    \param[in]  attribute_init_struct: MPU attribute initialization structure
                  attribute_number: attribute number
                                 MPU_ATTRIBUTE_NUMBERn (n=0,..,7)
                  memory_type: memory type
                                 MPU_MEMORY_DEVICE, MPU_MEMORY_NORMAL
                  outer_attributes: outer memory attributes
                                 MPU_OUTER_DEVICE
                                 MPU_NORMAL_OUTER_WT_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WT_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WT_TRAN_RW_ALLOC
                                 MPU_NORMAL_OUTER_NON_CACHEABLE
                                 MPU_NORMAL_OUTER_WB_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WB_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WB_TRAN_RW_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WT_NON_TRAN_RW_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_OUTER_WB_NON_TRAN_RW_ALLOC
                  inner_attributes: inner memory attributes
                                 MPU_NORMAL_INNER_WT_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WT_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WT_TRAN_RW_ALLOC
                                 MPU_NORMAL_INNER_NON_CACHEABLE
                                 MPU_NORMAL_INNER_WB_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WB_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WB_TRAN_RW_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WT_NON_TRAN_RW_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_NO_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_W_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_R_ALLOC
                                 MPU_NORMAL_INNER_WB_NON_TRAN_RW_ALLOC
                                 MPU_DEVICE_nGnRnE(for Device)
                                 MPU_DEVICE_nGnRE(for Device)
                                 MPU_DEVICE_nGRE(for Device)
                                 MPU_DEVICE_GRE(for Device)
    \param[out] none
    \retval     none
*/
void mpu_attribute_config(mpu_attribute_init_struct *attribute_init_struct)
{
    uint32_t attr_values;
    uint8_t  attr_x_value;

    __DMB();
    if(attribute_init_struct->attribute_number < MPU_ATTRIBUTE_NUMBER4) {
        /* configure MPU_MAIR0 */
        attr_values = MPU->MAIR0;
        attr_values &=  ~(0xFFUL << (attribute_init_struct->attribute_number * 8U));
        if(MPU_MEMORY_DEVICE == attribute_init_struct->memory_type) {
            attr_x_value = (attribute_init_struct->inner_attributes & 0x0CU);
        }else{
            attr_x_value = attribute_init_struct->inner_attributes | attribute_init_struct->outer_attributes;
        }
        attr_values |= ((uint32_t)attr_x_value  << (attribute_init_struct->attribute_number * 8U));
        MPU->MAIR0 = attr_values;
    } else {
        /* configure MPU_MAIR0 */
        attr_values = MPU->MAIR1;
        attr_values &=  ~(0xFFUL << ((attribute_init_struct->attribute_number -4U) * 8U));
        if(MPU_MEMORY_DEVICE == attribute_init_struct->memory_type) {
            attr_x_value = (attribute_init_struct->inner_attributes & 0x0CU);
        }else{
            attr_x_value = attribute_init_struct->inner_attributes | attribute_init_struct->outer_attributes;
        }
        attr_values |= ((uint32_t)attr_x_value  << ((attribute_init_struct->attribute_number - 4U) * 8U));
        MPU->MAIR1 = attr_values;
    }
}

/*!
    \brief      enable the MPU region
    \param[in]  none
    \param[out] none
    \retval     none
*/
void mpu_region_enable(void)
{
    MPU->RLAR |= MPU_RLAR_EN_Msk;
}

#endif /* __MPU_PRESENT */

______________________EXMC______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/EXMC/SDRAM/exmc_sdram.c

fix reason:
Comment update
V1.3.0:
    sdram_init_struct.burst_read_switch = ENABLE;
V1.4.0:
    sdram_init_struct.burst_read_switch = ENABLE;       /* NOTE: To support unaligned access, burst function must be disabled along with MPU */

______________________I2C______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/I2C/I2C3_Master_transmitter&slave_receiver_interrupt/readme.txt
../GD32F527_Firmware_Library/Examples/I2C/I2C3_Master_transmitter&slave_receiver_dma/readme.txt
../GD32F527_Firmware_Library/Examples/I2C/I2C3_Master_receiver&slave_transmitter_interrupt/readme.txt

fix reason:
Fixed the description issue of example readme.txt

V1.3.0:
  We should use the jumper to connect the PF14 and PF15. The PF1 and PF0 are 
connected as well.
V1.4.0:
  We should use the jumper to connect the PF14 and PF1. The PF15 and PF0 are 
connected as well.

______________________SAI______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_interrupt/main.c
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_dma/main.c
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_dma/readme.txt
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_interrupt/readme.txt



fix reason:
1. Only keep the Q clock for SAI, remove the redundant code for R and P, and change the main clock division of the SAI module from 16 to 4.
2. enable SAI Block0 master clock

V1.3.0:
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_interrupt/main.c
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_dma/main.c
void rcu_config(void)
{
...
    rcu_pllsai_p_config(60U, 2U);
    rcu_pllsai_q_config(60U, 6U);
    rcu_pllsai_r_config(60U, 6U);
...
}

../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_dma/readme.txt
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_interrupt/readme.txt
  Connect SAI_B0 FS PIN(PE2) to SAI_B1 FS PIN(PF7).
  Connect SAI_B0 SCK PIN(PE4) to SAI_B1 SCK PIN(PF9).
  Connect SAI_B0 SD PIN(PE5) to SAI_B1 SD PIN(PF8).
  Connect SAI_B0 SCK PIN(PD6) to SAI_B1 SCK PIN(PF6).

V1.4.0:
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_interrupt/main.c
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_dma/main.c
void rcu_config(void)
{
...
   rcu_pllsai_q_config(150U, 3U);
   rcu_sai_clock_config(RCU_SAISRC_PLLSAIQ);
...
}

../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_dma/readme.txt
../GD32F527_Firmware_Library/Examples/SAI/SAI_master_transmit_slave_receive_interrupt/readme.txt
  Connect SAI_B0 FS PIN(PE4) to SAI_B1 FS PIN(PF9).
  Connect SAI_B0 SCK PIN(PE5) to SAI_B1 SCK PIN(PF8).
  Connect SAI_B0 SD PIN(PD6) to SAI_B1 SD PIN(PF6).
  
  
______________________USB______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/USB/USB_Host/usb_host_msc_udisk/src/usbh_usr.c
../GD32F527_Firmware_Library/Examples/USB/USB_Device/dev_firmware_update/src/gd25qxx.c

fix reason:
1. The LED light flashes too quickly,increase the relevant delay time
2. The key logic does not match the actual circuit,modify the key judgment logic.

V1.3.0:
../GD32F527_Firmware_Library/Examples/USB/USB_Host/usb_host_msc_udisk/src/usbh_usr.c
int usbh_usr_msc_application(void)
{
...
        /* key Wakeup in polling */
        while((usbh_core.host.connect_status) && \
              (SET == gd_eval_key_state_get(KEY_WAKEUP))) {
            toggle_leds();
        }
...
}

static void toggle_leds(void)
{
    static uint32_t i;

    if(0x10000U == i++) {
        gd_eval_led_toggle(LED2);
        gd_eval_led_toggle(LED3);
        i = 0U;
    }
}

../GD32F527_Firmware_Library/Examples/USB/USB_Device/dev_firmware_update/src/gd25qxx.c
void spi_flash_init(void)
{
...
    /* quad wire SPI_IO2 and SPI_IO3 pin output enable */
    spi_quad_io23_output_enable(SPI5);
...
}

V1.4.0:
../GD32F527_Firmware_Library/Examples/USB/USB_Host/usb_host_msc_udisk/src/usbh_usr.c
int usbh_usr_msc_application(void)
{
...
        /* key Wakeup in polling */
        while((usbh_core.host.connect_status) && \
              (RESET == gd_eval_key_state_get(KEY_WAKEUP))) {
            toggle_leds();
        }
...
}
		
static void toggle_leds(void)
{
    static uint32_t i;

    if(0x80000U == i++) {
        gd_eval_led_toggle(LED2);
        gd_eval_led_toggle(LED3);
        i = 0U;
    }
}

../GD32F527_Firmware_Library/Examples/USB/USB_Device/dev_firmware_update/src/gd25qxx.c
void spi_flash_init(void)
{
...

...
}

______________________ADC______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/DAC/DAC_ADC_convert/main.c

fix reason:
added adc_clock_config(ADC_ADCCK_HCLK_DIV5) in function adc_config

V1.3.0:
void adc_config(void)
{
    /* ADC continous function enable */
    adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
	...
}
V1.4.0:
void adc_config(void)
{
    /* ADC clock config */
    adc_clock_config(ADC_ADCCK_HCLK_DIV5);
    /* ADC continous function enable */
    adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
	...
}
______________________SPI______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_spi.h
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_spi.c

fix reason:
This feature is not available in this chip so deleted the related API

V1.3.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_spi.h
#define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_spi.c
/*!
    \brief      enable SPI_IO2 and SPI_IO3 pin output
    \param[in]  spi_periph: SPIx(only x=5)
    \param[out] none
    \retval     none
*/
void spi_quad_io23_output_enable(uint32_t spi_periph)
{
    SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
}

/*!
   \brief      disable SPI_IO2 and SPI_IO3 pin output
   \param[in]  spi_periph: SPIx(only x=5)
   \param[out] none
   \retval     none
*/
void spi_quad_io23_output_disable(uint32_t spi_periph)
{
    SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
}

V1.4.0:


______________________PMU______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/PMU/Deepsleep_wakeup_RTC/main.c
../GD32F527_Firmware_Library/Examples/PMU/Deepsleep_wakeup_exti/main.c
../GD32F527_Firmware_Library/Examples/PMU/Standby_wakeup_RTC/main.c
../GD32F527_Firmware_Library/Examples/PMU/Standby_wakeup_pin/main.c

fix reason:
add switch frequence code to prevent vcore fluctuations

V1.3.0:

V1.4.0:
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

int main(void)
{
...
    while(1) {
...
        /* The following is to prevent Vcore fluctuations caused by frequency switching. 
           It is strongly recommended to include it to avoid issues caused by self-removal. */
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV2);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV4);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV8);
        _soft_delay_(0x50);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV16);
        _soft_delay_(0x50);
        rcu_system_clock_source_config(RCU_CKSYSSRC_IRC16M);
        _soft_delay_(200);
        rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV1);
...
    }
}

______________________RCU______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_rcu.h
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
../GD32F527_Firmware_Library/Examples/RCU/System_clock_switch/main.c


fix reason:
1. LXTAL was changed from bit1 to bit2
2. Overclocking limit modification

V1.3.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_rcu.h
#define RCU_BDCTL_LXTALDRI              BIT(3)                    /*!< LXTAL drive capability */

/* LXTAL drive capability */
#define RCU_LXTALDRI_LOWER_DRIVE        ((uint32_t)0x00000000)             /*!< LXTAL drive capability is selected lower */
#define RCU_LXTALDRI_HIGHER_DRIVE       RCU_BDCTL_LXTALDRI                 /*!< LXTAL drive capability is selected higher */

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
/*!
    \brief      configure the LXTAL drive capability
    \param[in]  lxtal_dricap: drive capability of LXTAL
                only one parameter can be selected which is shown as below:
      \arg        RCU_LXTALDRI_LOWER_DRIVE: lower driving capability
      \arg        RCU_LXTALDRI_HIGHER_DRIVE: higher driving capability
    \param[out] none
    \retval     none
*/
../GD32F527_Firmware_Library/Examples/RCU/System_clock_switch/main.c
    /* APB1 = AHB */
    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;

V1.4.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_rcu.h
#define RCU_BDCTL_LXTALDRI              BITS(3,4)                 /*!< LXTAL drive capability */

/* LXTAL drive capability */
#define BDCTL_LXTALDRI(regval)          (BITS(3,4) & ((uint32_t)(regval) << 3))
#define RCU_LXTALDRI_LOWER_DRIVE        BDCTL_LXTALDRI(0)                  /*!< LXTAL drive capability is selected lower */
#define RCU_LXTALDRI_MED_LOWER_DRIVE    BDCTL_LXTALDRI(1)                  /*!< LXTAL drive capability is selected medium lower */
#define RCU_LXTALDRI_MED_HIGHER_DRIVE   BDCTL_LXTALDRI(2)                  /*!< LXTAL drive capability is selected medium higher */
#define RCU_LXTALDRI_HIGHER_DRIVE       BDCTL_LXTALDRI(3)                  /*!< LXTAL drive capability is selected higher */


../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
/*!
    \brief      configure the LXTAL drive capability
    \param[in]  lxtal_dricap: drive capability of LXTAL
                only one parameter can be selected which is shown as below:
      \arg        RCU_LXTALDRI_LOWER_DRIVE: lower driving capability
      \arg        RCU_LXTALDRI_MED_LOWER_DRIVE: medium lower driving capability
      \arg        RCU_LXTALDRI_MED_HIGHER_DRIVE: medium higher driving capability
      \arg        RCU_LXTALDRI_HIGHER_DRIVE: higher driving capability
    \param[out] none
    \retval     none
*/

../GD32F527_Firmware_Library/Examples/RCU/System_clock_switch/main.c
    /* APB1 = AHB */
    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;

______________________RCU______________________________________________________________________________________________



fix reason:


V1.3.0:



V1.4.0:

______________________RCU______________________________________________________________________________________________



fix reason:


V1.3.0:



V1.4.0:


______________________RCU______________________________________________________________________________________________



fix reason:


V1.3.0:



V1.4.0:


______________________RCU______________________________________________________________________________________________



fix reason:


V1.3.0:



V1.4.0:


______________________RCU______________________________________________________________________________________________



fix reason:


V1.3.0:



V1.4.0:

______________________RCU______________________________________________________________________________________________



fix reason:


V1.3.0:



V1.4.0:




******************* V1.3.0 2025-08-08 ******************************************************************************************
______________________USB______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/device/core/Source/usbd_core.c
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/device/core/Source/usbd_enum.c

fix reason:
FAIL occurred during the CVTest for a self-powered device, improve the recording and handling of self-powered device information.

V1.2.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/device/core/Source/usbd_core.c
void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core)
{
    udev->dev.desc = desc;

    /* class callbacks */
    udev->dev.class_core = class_core;

    /* create serial string */
    serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]);

    /* configure USB capabilities */
    (void)usb_basic_init(&udev->bp, &udev->regs, core);
	...
}	
	
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/device/core/Source/usbd_enum.c
static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req)
{
    uint8_t recp = BYTE_LOW(req->wIndex);
    usb_reqsta req_status = REQ_NOTSUPP;
    usb_transc *transc = &udev->dev.transc_in[0];

    static uint8_t status[2] = {0};

    switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) {
    case USB_RECPTYPE_DEV:
        if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \
                ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) {

            if(udev->dev.pm.power_mode) {
                status[0] = USB_STATUS_SELF_POWERED;
            } else {
                status[0] = 0U;
            }

            if(udev->dev.pm.dev_remote_wakeup) {
                status[0] |= USB_STATUS_REMOTE_WAKEUP;
            } else {
                status[0] = 0U;
            }

            req_status = REQ_SUPP;
        }
        break;
		...
}

V1.3.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/device/core/Source/usbd_core.c
void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core)
{
    udev->dev.desc = desc;

    /* class callbacks */
    udev->dev.class_core = class_core;

    /* create serial string */
    serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]);

    /* configure power management */
    udev->dev.pm.power_mode = (udev->dev.desc->config_desc[7] & BIT(6)) >> 6;

    /* configure USB capabilities */
    (void)usb_basic_init(&udev->bp, &udev->regs, core);
	...
}
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/device/core/Source/usbd_enum.c
static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req)
{
    uint8_t recp = BYTE_LOW(req->wIndex);
    usb_reqsta req_status = REQ_NOTSUPP;
    usb_transc *transc = &udev->dev.transc_in[0];

    static uint8_t status[2] = {0};

    switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) {
    case USB_RECPTYPE_DEV:
        if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \
                ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) {

            if(udev->dev.pm.power_mode) {
                status[0] = USB_STATUS_SELF_POWERED;
            } else {
                status[0] = 0U;
            }

            if(udev->dev.pm.dev_remote_wakeup) {
                status[0] |= USB_STATUS_REMOTE_WAKEUP;
            }

            req_status = REQ_SUPP;
        }
        break;
		...
}

______________________RCU______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_rcu.h
fix reason:
Add the PLLI2SQ_DIV parameter
V1.2.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_rcu.h
/* RCU_CFG1 */
#define RCU_CFG1_PLLSAIRDIV             BITS(16,17)               /*!< the divider factor from PLLSAIR clock */

/* RCU_SAISEL */
#define RCU_CFG1_SAISEL                 BITS(20,21)               /*!< SAI clock selection */
#define RCU_CFG1_TIMERSEL               BIT(24)                   /*!< TIMER clock selection *

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
/*!
    \brief      configure the PLLI2S_Q clock
    \param[in]  plli2s_n: the PLLI2S VCO clock multi factor
      \arg        this parameter should be selected between 50 and 500
    \param[in]  plli2s_q: the PLLI2S Q output frequency division factor from PLLI2S VCO clock
      \arg        this parameter should be selected between 2 and 15
    \param[out] none
    \retval     ErrStatus: SUCCESS or ERROR
*/
ErrStatus rcu_plli2s_q_config(uint32_t plli2s_n, uint32_t plli2s_q)
{
    /* check the function parameter */
    if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_Q_VALID(plli2s_q)) {
        RCU_PLLI2S = (plli2s_n << 6) | (plli2s_q << 24);
    } else {
        /* return status */
        return ERROR;
    }

    /* return status */
    return SUCCESS;
}

V1.3.0:
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_rcu.h
/* RCU_CFG1 */
#define RCU_CFG1_PLLI2SQDIV             BITS(0,4)                 /*!< the divider factor from PLLI2SQ clock */
#define RCU_CFG1_PLLSAIRDIV             BITS(16,17)               /*!< the divider factor from PLLSAIR clock */
#define RCU_CFG1_SAISEL                 BITS(20,21)               /*!< SAI clock selection */
#define RCU_CFG1_TIMERSEL               BIT(24)                   /*!< TIMER clock selection */

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_rcu.c
/*!
    \brief      configure the PLLI2S_Q clock
    \param[in]  plli2s_n: the PLLI2S VCO clock multi factor
      \arg        this parameter should be selected between 50 and 500
    \param[in]  plli2s_q: the PLLI2S Q output frequency division factor from PLLI2S VCO clock
      \arg        this parameter should be selected between 2 and 15
    \param[in]  plli2s_q_div: the PLLI2S_Q output frequency division factor from PLLI2S Q clock
      \arg        RCU_PLLI2SQ_DIVx(x = 1, 2, 3, ... , 32): PLLI2SQ divided x used as input of CK_PLLI2SQ
    \param[out] none
    \retval     ErrStatus: SUCCESS or ERROR
*/
ErrStatus rcu_plli2s_q_config(uint32_t plli2s_n, uint32_t plli2s_q, uint32_t plli2s_q_div)
{
    uint32_t reg;

    reg = RCU_CFG1;
    /* reset the PLLI2SQDIV bit and set according to plli2s_q_div */
    reg &= ~RCU_CFG1_PLLI2SQDIV;

    /* check the function parameter */
    if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_Q_VALID(plli2s_q)) {
        RCU_PLLI2S = (plli2s_n << 6) | (plli2s_q << 24);
        RCU_CFG1 = (reg | plli2s_q_div);
    } else {
        /* return status */
        return ERROR;
    }

    /* return status */
    return SUCCESS;
}

______________________TLI______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_tli.c
fix reason:
Correct annotation errors:LAYER_PPF_ARG1555 --> LAYER_PPF_ARGB1555
V1.2.0:
                  layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565,
                                 LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8,
V1.3.0:
                  layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565,
                                 LAYER_PPF_ARGB1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8,

______________________I2C______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_i2c.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_i2c.h
fix reason:
NACKEN does not support software clearing, so the software clearing NACKEN interface in the firmware library needs to be removed.
V1.2.0:
/*!
    \brief      generate an ACK in slave mode
    \param[in]  i2c_add_periph: I2Cx(x=3,4,5)
    \param[out] none
    \retval     none
*/
void i2c_add_nack_disable(uint32_t i2c_add_periph)
{
    I2C_ADD_CTL1(i2c_add_periph) &= ~I2C_ADD_CTL1_NACKEN;
}
V1.3.0:

______________________I2C______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/I2C/Master_receiver&slave_transmitter/main.c
fix reason:
Change from master transmit-slave receive to master receive-slave transmit.
V1.2.0:
   /* send slave address to I2C bus*/
    i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_TRANSMITTER);

    /* wait until ADDSEND bit is set*/
    while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND));
    while(!i2c_flag_get(I2C1, I2C_FLAG_ADDSEND));
    /* clear ADDSEND bit */
    i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
    i2c_flag_clear(I2C1, I2C_FLAG_ADDSEND);
    for(i = 0; i < 16; i++) {
        /* send a data byte */
        i2c_data_transmit(I2C0, i2c_transmitter[i]);
        /* wait until the transmission data register is empty*/
        while(!i2c_flag_get(I2C0, I2C_FLAG_TBE));
        /* wait until the RBNE bit is set */
        while(!i2c_flag_get(I2C1, I2C_FLAG_RBNE));
        /* read a data from I2C_DATA */
        i2c_receiver[i] = i2c_data_receive(I2C1);
    }
    /* send a stop condition to I2C bus*/
    i2c_stop_on_bus(I2C0);
    /* wait until stop condition generate */
    while(I2C_CTL0(I2C0) & I2C_CTL0_STOP);
    while(!i2c_flag_get(I2C1, I2C_FLAG_STPDET));
    /* clear the STPDET bit */
    i2c_enable(I2C1);
    state = memory_compare(i2c_transmitter, i2c_receiver, 16);
    if(SUCCESS == state) {
        gd_eval_led_on(LED1);
        gd_eval_led_on(LED2);
    } else {
        gd_eval_led_off(LED1);
        gd_eval_led_off(LED2);
    }

V1.3.0:
    /* send slave address to I2C bus*/
    i2c_master_addressing(I2C0, I2C1_SLAVE_ADDRESS7, I2C_RECEIVER);

    /* wait until ADDSEND bit is set*/
    while(!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND));
    while(!i2c_flag_get(I2C1, I2C_FLAG_ADDSEND));
    /* clear ADDSEND bit */
    i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
    i2c_flag_clear(I2C1, I2C_FLAG_ADDSEND);
    for(i = 0; i < 15; i++) {
        /* send a data byte */
        i2c_data_transmit(I2C1, i2c_transmitter[i]);
        /* wait until the transmission data register is empty */
        while(!i2c_flag_get(I2C1, I2C_FLAG_TBE));
        /* wait until the RBNE bit is set */
        while(!i2c_flag_get(I2C0, I2C_FLAG_RBNE));
        /* read a data from I2C_DATA */
        i2c_receiver[i] = i2c_data_receive(I2C0);
    }
    /* send a NACK for the last data byte */
    i2c_ack_config(I2C0, I2C_ACK_DISABLE);
    /* send a data byte */
    i2c_data_transmit(I2C1, i2c_transmitter[i]);
    /* wait until the transmission data register is empty */
    while(!i2c_flag_get(I2C1, I2C_FLAG_TBE));
    /* the master doesn't acknowledge for the last byte */
    while(!i2c_flag_get(I2C1, I2C_FLAG_AERR));
    /* send a stop condition to I2C bus */
    i2c_stop_on_bus(I2C0);
    while(I2C_CTL0(I2C0) & I2C_CTL0_STOP);
    i2c_receiver[i] = i2c_data_receive(I2C0);
    i2c_ack_config(I2C0, I2C_ACK_ENABLE);
    /* clear the bit of AERR */
    i2c_flag_clear(I2C1, I2C_FLAG_AERR);

    /* compare the transmit buffer and the receive buffer */
    state = memory_compare(i2c_transmitter, i2c_receiver, 16);
    /* if success, LED1 and LED2 are on */
    if(SUCCESS == state) {
        gd_eval_led_on(LED1);
        gd_eval_led_on(LED2);
    } else {
        /* if failed, LED1 and LED2 are off */
        gd_eval_led_off(LED1);
        gd_eval_led_off(LED2);
    }
______________________ADC______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/ADC
../GD32F527_Firmware_Library/Examples/ADC
fix reason:
Bug fix
V1.2.0:
../GD32F527_Firmware_Library/Examples/ADC/ADC0_software_trigger_routine_channel_polling/main.c
void rcu_config(void)
{
    /* enable GPIOA clock */
    rcu_periph_clock_enable(RCU_GPIOA);
    /* enable ADC clock */
    rcu_periph_clock_enable(RCU_ADC0);
    /* config ADC clock */
    adc_clock_config(ADC_ADCCK_PCLK2_DIV8);
}

void adc_config(void)
{
    /* reset ADC */
    adc_deinit();
    /* ADC mode config */
    adc_sync_mode_config(ADC_SYNC_MODE_INDEPENDENT);
	...
	
}
../GD32F527_Firmware_Library/Examples/ADC/ADC1_analog_watchdog/main.c
../GD32F527_Firmware_Library/Examples/ADC/ADC1_resolution_oversample/main.c
void rcu_config(void)
{
    /* enable GPIOA clock */
    rcu_periph_clock_enable(RCU_GPIOA);
    /* enable ADC clock */
    rcu_periph_clock_enable(RCU_ADC1);
    /* config ADC clock */
    adc_clock_config(ADC_ADCCK_PCLK2_DIV8);
}

../GD32F527_Firmware_Library/Examples/ADC/ADC1_resolution_oversample/main.c
../GD32F527_Firmware_Library/Examples/ADC/ADC0_EXTI_trigger_routine_sequence/main.c
    /* ADC trigger config */
    adc_external_trigger_source_config(ADC0, ADC_ROUTINE_CHANNEL, ADC_EXTTRIG_ROUTINE_EXTI_11);
    adc_external_trigger_config(ADC0, ADC_ROUTINE_CHANNEL, ENABLE);

V1.3.0:
../GD32F527_Firmware_Library/Examples/ADC/ADC1_analog_watchdog/main.c
../GD32F527_Firmware_Library/Examples/ADC/ADC1_resolution_oversample/main.c
void rcu_config(void)
{
    /* enable GPIOA clock */
    rcu_periph_clock_enable(RCU_GPIOA);
    /* enable ADC clock */
    rcu_periph_clock_enable(RCU_ADC0);
    /* enable ADC clock */
    rcu_periph_clock_enable(RCU_ADC1);
    /* config ADC clock */
    adc_clock_config(ADC_ADCCK_PCLK2_DIV8);
}

../GD32F527_Firmware_Library/Examples/ADC/ADC0_software_trigger_routine_channel_polling/main.c
void rcu_config(void)
{
    /* enable GPIOA clock */
    rcu_periph_clock_enable(RCU_GPIOA);
    /* enable ADC clock */
    rcu_periph_clock_enable(RCU_ADC0);
}

void adc_config(void)
{
    /* reset ADC */
    adc_deinit();
    /* config ADC clock */
    adc_clock_config(ADC_ADCCK_PCLK2_DIV8);
    /* ADC mode config */
    adc_sync_mode_config(ADC_SYNC_MODE_INDEPENDENT);
	...
}

../GD32F527_Firmware_Library/Examples/ADC/ADC1_resolution_oversample/main.c
../GD32F527_Firmware_Library/Examples/ADC/ADC0_EXTI_trigger_routine_sequence/main.c
    /* ADC trigger config */
    adc_external_trigger_source_config(ADC0, ADC_ROUTINE_CHANNEL, ADC_EXTTRIG_ROUTINE_EXTI_11);
    adc_external_trigger_config(ADC0, ADC_ROUTINE_CHANNEL, EXTERNAL_TRIGGER_RISING);

______________________USART______________________________________________________________________________________________
../GD32F527_Firmware_Library/Examples/USART/Half_duplex_transmitter&receiver/main.c
fix reason:
Change GPIO mode from GPIO_OTYPE_PP to GPIO_OTYPE_OD
V1.2.0:
    /* configure USART0 TX as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
    /* configure USART1 TX as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
V1.3.0:
    /* configure USART0 TX as alternate function open drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
    /* configure USART1 TX as alternate function open drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
	
______________________USB______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/driver/Source/drv_usb_dev.c
fix reason:
Fix the issue where the enum_speed parameter may cause an array out-of-bounds error.
Shift the value of enum_speed after obtaining the ES bit field.
V1.2.0:
    uint32_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
V1.3.0:
    uint32_t enum_speed = ((udev->regs.dr->DSTAT & DSTAT_ES) >> 1);
______________________PMU______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_pmu.c
fix reason:
pmu_to_sleepmode update enter sleep mode ,add  __SEV(); __WFE();
V1.2.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __WFE();
        __WFE();
    }
}
V1.3.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
    /* clear sleepdeep bit of Cortex-M33 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

    /* select WFI or WFE command to enter sleep mode */
    if(WFI_CMD == sleepmodecmd) {
        __WFI();
    } else {
        __SEV();
        __WFE();
        __WFE();
    }
}

______________________CAN______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_can.c
fix reason:
When the number of bytes sent by CAN exceeds 8, the frame sent by CAN to the bus will have a problem.
Add a limit to the code, set to 8 when the number of bytes exceeds 8
V1.2.0:
    if(CAN_FDF_CLASSIC == transmit_message->fd_flag) {
        /* set the data length */
		CAN_TMP(can_periph, mailbox_number) &= ~(CAN_TMP_DLENC | CAN_TMP_ESI | CAN_TMP_BRS | CAN_TMP_FDF);
        ...
    }
V1.3.0:
    if(CAN_FDF_CLASSIC == transmit_message->fd_flag) {
        /* set the data length */
        CAN_TMP(can_periph, mailbox_number) &= ~(CAN_TMP_DLENC | CAN_TMP_ESI | CAN_TMP_BRS | CAN_TMP_FDF);
        
        /* Classic CAN frame data lenth does not exceed 8 */
        if (transmit_message->tx_dlen > 8U) {
            transmit_message->tx_dlen = 8U;
        }
        ...
    } 

______________________PKCAU______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f5xx_pkcau.c
fix reason:
update Resolve MISRA Issues
V1.2.0:
    /* read data from PKCAU RAM which is not a multiple of four */
    if(size > 0U) {
        data = *(uint32_t *)((uint32_t)(PKCAU_BASE + offset + i));
        for(j = 0U; j < size; j++) {
            buf[j] = (uint8_t)((data >> ((size - 1U - j) * 8U)) & 0xffU);
        }
    }
V1.3.0:
    /* read data from PKCAU RAM which is not a multiple of four */
    if(size > 0U) {
        data = *(uint32_t *)((uint32_t)(PKCAU_BASE + offset + i));
        for(j = 0U; j < size; j++) {
            buf[j] = (uint8_t)((data >> (((size - 1U - j) & 0x03U) * 8U)) & 0xffU);
        }
    }
______________________Common______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/CMSIS/GD/GD32F527/Source/system_gd32f527.c
fix reason:
The software delay of the cut frequency function has some problems, so the position of the function needs to be adjusted
V1.2.0:
    _soft_delay_(200);
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    
V1.3.0:
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    _soft_delay_(200);

______________________I2C______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F5xx_standard_peripheral/Include/gd32f5xx_i2c_add.h
../GD32F527_Firmware_Library/Firmware/GD32F5xx_standard_peripheral/Source/gd32f5xx_i2c_add.c
fix reason:
i2c_add_transfer_byte_number_config(uint32_t i2c_add_periph, uint32_t byte_number) modify to i2c_add_transfer_byte_number_config(uint32_t i2c_add_periph, uint8_t byte_number)
V1.2.0:
void i2c_add_transfer_byte_number_config(uint32_t i2c_add_periph, uint32_t byte_number)

V1.3.0:
void i2c_add_transfer_byte_number_config(uint32_t i2c_add_periph, uint8_t byte_number)


******************* V1.2.0 2024-12-20 ******************************************************************************************
______________________MISC______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_misc.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_misc.h
fix reason:
The first parameter type of the nvic_irq_enable/disable function has been changed from uint8_t to IRQn_Type.
V1.1.0:
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
void nvic_irq_disable(uint8_t nvic_irq)
V1.2.0:
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
void nvic_irq_disable(IRQn_Type nvic_irq)

______________________Common______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/CMSIS/GD/GD32F527/Source/system_gd32f527.c
fix reason:
Add the clock cutting patch to the clock configuration function, and modify the corresponding example. The function test is normal
V1.1.0:
#define RCU_MODIFY(__delay)     do{                                     \
                                    volatile uint32_t i;                \
                                    if(0U != __delay){                   \
                                        RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
                                        for(i=0U; i<__delay; i++){       \
                                        }                               \
                                        RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
                                        for(i=0U; i<__delay; i++){       \
                                        }                               \
                                    }                                   \
                                }while(0)
								
								
								
V1.2.0:
/* The following is to prevent Vcore fluctuations caused by frequency switching. 
   It is strongly recommended to include it to avoid issues caused by self-removal. */
#define RCU_MODIFY_4(__delay)   do{                                     \
                                    volatile uint32_t i, reg;           \
                                    if(0 != __delay){                   \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV2;      \
                                        /* AHB = SYSCLK/2 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV4;      \
                                        /* AHB = SYSCLK/4 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV8;      \
                                        /* AHB = SYSCLK/8 */            \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                        reg = RCU_CFG0;                 \
                                        reg &= ~(RCU_CFG0_AHBPSC);      \
                                        reg |= RCU_AHB_CKSYS_DIV16;     \
                                        /* AHB = SYSCLK/16 */           \
                                        RCU_CFG0 = reg;                 \
                                        /* Insert a software delay */   \
                                        for(i=0; i<__delay; i++){       \
                                        }                               \
                                    }                                   \
                                }while(0)
								
/* software delay to prevent the impact of Vcore fluctuations.
   It is strongly recommended to include it to avoid issues caused by self-removal. */
static void _soft_delay_(uint32_t time)
{
    __IO uint32_t i;
    for(i=0; i<time*10; i++){
    }
}

V1.1.0:
    RCU_MODIFY(0x50U);
V1.2.0:
    if(((RCU_CFG0 & RCU_CFG0_SCSS) == RCU_SCSS_PLLP)){
        RCU_MODIFY_4(0x50);
    }
    _soft_delay_(200);

V1.1.0:
    /* select PLL as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
V1.2.0:
    reg_temp = RCU_CFG0;
    /* select PLL as system clock */
    reg_temp &= ~RCU_CFG0_SCS;
    reg_temp |= RCU_CKSYSSRC_PLLP;
    RCU_CFG0 = reg_temp;
______________________I2C_________________________________________________________________________________________________

../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Source/gd32f527_i2c.c
../GD32F527_Firmware_Library/Firmware/GD32F527_standard_peripheral/Include/gd32f527_i2c.h
fix reason:
add bit15 RBNECM in I2C_CTL1 register and add function i2c_rbne_clear_config
V1.1.0:
/*!
    \brief      configure RBNE clear condition
    \param[in]  i2c_periph: I2Cx(x=0,1,2)
    \param[in]  rbnecondition:
                only one parameter can be selected which is shown as below:
      \arg        I2C_CFGRBNE_ON: RBNE can be cleared when RDATA is read
      \arg        I2C_CFGRBNE_OFF: RBNE can be cleared when RDATA is read and BTC is cleared
    \param[out] none
    \retval     none
*/
void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t rbnecondition)
{
    /* configure rbne clear condition  */
    uint32_t ctl = 0U;

    ctl = I2C_CTL1(i2c_periph);
    ctl &= ~(I2C_CTL1_CFGRBNE);
    ctl |= rbnecondition;
    I2C_CTL1(i2c_periph) = ctl;
}
V1.2.0:
/*!
    \brief      configure RBNE clear mode
    \param[in]  i2c_periph: I2Cx(x=0,1,2)
    \param[in]  mode:
                only one parameter can be selected which is shown as below:
      \arg        I2C_RBNE_CLEAR_BTC_0: RBNE can be cleared when I2C_DATA is read and BTC is cleared
      \arg        I2C_RBNE_CLEAR: RBNE can be cleared when I2C_DATA is read
    \param[out] none
    \retval     none
*/
void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode)
{
    /* configure RBNE clear mode */
    uint32_t ctl = 0U;

    ctl = I2C_CTL1(i2c_periph);
    ctl &= ~(I2C_CTL1_RBNECM);
    ctl |= mode;
    I2C_CTL1(i2c_periph) = ctl;
}

V1.1.0
/* RBNE clear condition control */
#define I2C_CFGRBNE_OFF                ((uint32_t)0x00000000U)          /*!< RBNE can be cleared when RXDATA is read and BTC is cleared */
#define I2C_CFGRBNE_ON                 I2C_CTL1_CFGRBNE                 /*!< RBNE can be cleared when RXDATA is read */

V1.2.0:
/* RBNE clear mode */
#define I2C_RBNE_CLEAR_BTC_0             ((uint32_t)0x00000000U)               /*!< RBNE can be cleared when I2C_DATA is read and BTC is cleared */
#define I2C_RBNE_CLEAR                   I2C_CTL1_RBNECM                       /*!< RBNE can be cleared when I2C_DATA is read */

______________________Common______________________________________________________________________________________________
../GD32F527_Firmware_Library/Firmware/CMSIS/GD/GD32F527/Source/ARM/startup_gd32f527.s
../GD32F527_Firmware_Library/Firmware/CMSIS/GD/GD32F527/Source/IAR/startup_gd32f527.s
fix reason:Added TCMSRAM & SRAM initialization in startup code
V1.1.0:
Reset_Handler   PROC
                EXPORT  Reset_Handler                     [WEAK]
                IMPORT  SystemInit
                IMPORT  __main
                IMPORT |Image$$RW_IRAM1$$RW$$Base|

                LDR     R0, =|Image$$RW_IRAM1$$RW$$Base|
                ADD     R1, R0, #0x8000
                LDR     R2, =0x0
MEM_INIT        STRD    R2, R2, [ R0 ] , #8
                CMP     R0, R1
                BNE     MEM_INIT

                LDR     R0, =SystemInit
                BLX     R0
                LDR     R0, =__main
                BX      R0
                ENDP
V1.2.0:
Reset_Handler   PROC
                EXPORT  Reset_Handler                     [WEAK]

                LDR     R0, =0x10000000
                MOV     R1, #64
                LSL     R1, R1, #10
                MOV     R2, #0x00
TCMSRAM_INIT    STM     R0!, {R2}
                SUBS    R1, R1, #4
                CMP     R1, #0x00
                BNE     TCMSRAM_INIT

                LDR     R0, =0x1FFF7A20
                LDR     R2, [R0]
                SUBS    R2, R2, #64
                LDR     R0, = 0x0000FFFF
                AND     R2, R2, R0
                LSL     R2, R2, #10
                LDR     R1, =0x20000000
                MOV     R0, #0x00
SRAM_INIT       STM     R1!, {R0}
                SUBS    R2, R2, #4
                CMP     R2, #0x00
                BNE     SRAM_INIT

                IMPORT  SystemInit
                IMPORT  __main
                LDR     R0, =SystemInit
                BLX     R0
                LDR     R0, =__main
                BX      R0
                ENDP
______________________USB______________________________________________________________________________________________
Fix file:
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/host/core/Source/usbh_core.c
fix reason:
Due to interrupts or the limitation on the number of endpoints, executing functions related to uhost->active_class without 
it being assigned an address can cause the program to enter a hard fault 
V1.1.0:
    case HOST_ERROR:
        /* deinitialize host for new enumeration */
        usbh_deinit(uhost);
        uhost->usr_cb->dev_deinit();
        uhost->active_class->class_deinit(uhost);
        break;

    case HOST_DEV_DETACHED:
        /* manage user disconnect operations*/
        uhost->usr_cb->dev_detach();

        /* re-initialize host for new enumeration */
        usbh_deinit(uhost);
        uhost->usr_cb->dev_deinit();
        uhost->active_class->class_deinit(uhost);
        usbh_pipe_delete(&usbh_core);
        uhost->cur_state = HOST_DEFAULT;
        break;
V1.2.0:
    case HOST_ERROR:
        /* deinitialize host for new enumeration */
        usbh_deinit(uhost);
        uhost->usr_cb->dev_deinit();
        if(NULL != uhost->active_class) {
            uhost->active_class->class_deinit(uhost);
        }
        break;

    case HOST_DEV_DETACHED:
        /* manage user disconnect operations*/
        uhost->usr_cb->dev_detach();

        /* re-initialize host for new enumeration */
        usbh_deinit(uhost);
        uhost->usr_cb->dev_deinit();
        if(NULL != uhost->active_class) {
            uhost->active_class->class_deinit(uhost);
        }
        usbh_pipe_delete(&usbh_core);
        uhost->cur_state = HOST_DEFAULT;
        break;

Fix file:
../GD32F527_Firmware_Library/Firmware/GD32F527_usb_library/driver/Source/drv_usbh_int.c
fix reason:
The original firmware library was used to control transfers and bulk transfers through the software Halt channel.
After the problem of customer project, the DMA mode of IC feedback host will automatically Halt, and the code only needs to re-enable the channel.
V1.1.0:
        case USB_EPTYPE_BULK:
            usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF);

            pp->data_toggle_in ^= 1U;
            break;
V1.2.0:
        case USB_EPTYPE_BULK:
            if(USB_USE_DMA == udev->bp.transfer_mode) {
                udev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE;
            } else {
                usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF);
            }

            pp->data_toggle_in ^= 1U;
            break;


______________________I2C______________________________________________________________________________________________
Fix file:
../GD32F527_Firmware_Library/Examples/I2C/I2C3_deepsleep_wakeup/I2C_IE.c
fix reason: Bug fix
V1.1.0:
void i2c3_event_irq_handler(void)
{
    if(i2c_add_interrupt_flag_get(I2C3, I2C_ADD_INT_FLAG_ADDSEND)) {
        /* clear the ADDSEND bit */
        i2c_add_interrupt_flag_clear(I2C3, I2C_ADD_INT_FLAG_ADDSEND);
    } else if(i2c_add_interrupt_flag_get(I2C3, I2C_ADD_INT_FLAG_RBNE)) {
        /* if reception data register is not empty ,I2C3 will read a data from I2C_RDATA */
        *i2c_rxbuffer++ = i2c_data_receive(I2C3);
    } else if(i2c_add_interrupt_flag_get(I2C3, I2C_ADD_INT_FLAG_STPDET)) {
        /* clear STPDET interrupt flag */
        i2c_add_interrupt_flag_clear(I2C3, I2C_ADD_INT_FLAG_STPDET);
        /* disable I2C3 interrupt */
        i2c_add_interrupt_disable(I2C3, I2C_ADD_INT_ERR | I2C_ADD_INT_STPDET | I2C_ADD_INT_ADDM | I2C_ADD_INT_RBNE);
    }
}
V1.2.0:
void i2c3_event_irq_handler(void)
{
    if(i2c_add_interrupt_flag_get(I2C3, I2C_ADD_INT_FLAG_ADDSEND)) {
        /* clear the ADDSEND bit */
        i2c_add_interrupt_flag_clear(I2C3, I2C_ADD_INT_FLAG_ADDSEND);
    } else if(i2c_add_interrupt_flag_get(I2C3, I2C_ADD_INT_FLAG_RBNE)) {
        /* if reception data register is not empty ,I2C3 will read a data from I2C_RDATA */
        *i2c_rxbuffer++ = i2c_add_data_receive(I2C3);
    } else if(i2c_add_interrupt_flag_get(I2C3, I2C_ADD_INT_FLAG_STPDET)) {
        /* clear STPDET interrupt flag */
        i2c_add_interrupt_flag_clear(I2C3, I2C_ADD_INT_FLAG_STPDET);
        /* disable I2C3 interrupt */
        i2c_add_interrupt_disable(I2C3, I2C_ADD_INT_ERR | I2C_ADD_INT_STPDET | I2C_ADD_INT_ADDM | I2C_ADD_INT_RBNE);
    }
}

______________________HAU______________________________________________________________________________________________
Fix file:
../GD32F527_Firmware_Library/Examples/HAU/Hash_SHA224_SHA256_dma/Expected_Results.txt
fix reason: 
V1.1.0:
message to be hashed:

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.  

SHA224 message digest (224 bits):

0x4bffa841    
0xf03820b1    
0xc363595e    
0x12cf5d85    
0x3a63a3ae    
0x934bc182    
0x477d49f5    
  

SHA256 message digest (256 bits):

0xa51b72b6    
0x8223bb84    
0x33325bb    
0x34ca08f8    
0x846e825e    
0xb39cdce0    
0x58797f0a    
0x9316c520  

V1.2.0:
message input:

CHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor IncCHN GigaDevice Semiconductor Inc  

SHA224 message digest (224 bits):

 0xD3 0x91 0x8F 0x90
 0x2E 0xB5 0xDC 0x54
 0x2D 0xEB 0x4A 0x7D
 0x48 0x62 0x27 0x37
 0x7F 0x06 0x24 0x6E
 0xBF 0x05 0x99 0xF9
 0x53 0xF9 0x38 0xF7
  

SHA256 message digest (256 bits):

 0xC6 0x43 0xD7 0x88
 0xA2 0x91 0x05 0x61
 0xEF 0xFC 0xFA 0xD8
 0x5D 0x95 0xCC 0x43
 0x7B 0x9E 0x1E 0x18
 0x51 0x97 0x3A 0x41
 0x60 0xDB 0xE5 0xFC
 0xA1 0x26 0x42 0xB5
 
______________________ENET______________________________________________________________________________________________
Fix file:
../GD32F527_Firmware_Library/Examples/ENET/Telnet/inc/lwipopts.h
fix reason: Turn off the LWIP debug functionality by default.
V1.1.0:
/* Lwip debug options */
#define LWIP_DEBUG              1
V1.2.0:
/* Lwip debug options */
#define LWIP_DEBUG              0

******************* V1.1.0 2024-06-07 ******************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
gd32F527_it.c
fix reason:
The single bit ECC error and FPU interrupts are enabled  by default, so an interrupt service function needs to be added.
V1.0.0:
none
V1.1.0:
#define SINGLE_ECC_ERROR_HANDLE(s)   do{}while(1)
/*!
    \brief    this function handles SRAM and Flash single bit ECC non-correction exception
    \param[in]  none
    \param[out] none
    \retval     none
*/
void SYSCFG_SINGLE_BIT_ECC_ER_IRQHandler(void)
{
    if((SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE0)) ||
            (SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE1)) ||
            (SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE2)) ||
            (SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE3)) ||
            (SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE4)) ||
            (SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE5)) ||
            (SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_ECCSE6))) {
        MULTI_ECC_ERROR_HANDLE("SRAM or FLASH single bit ECC error\r\n");
    }
}

/*!
    \brief    this function handles FPU exception
    \param[in]  none
    \param[out] none
    \retval     none
*/
void FPU_IRQHandler(void)
{
    /* if FPU exception occurs, go to infinite loop */
    while(1) {
    }
}

Fix file:
gd32F527_it.h
fix reason:
Add the declaration of the SYSCFG_SINGLE_BIT_ECC_ER_IRQHandler and FPU_IRQHandler function. 
V1.0.0:
none
V1.1.0:
/* this function handles SRAM and Flash single bit ECC non-correction exception */
void SYSCFG_SINGLE_BIT_ECC_ER_IRQHandler(void);
/* this function handles FPU exception */
void FPU_IRQHandler(void);

Fix file:
All functions in the file that involve the use of a serial port.
fix reason:
Modify the serial port redirection function to adapt to the Embedded Builder IDE.
V1.0.0:
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
    return ch;
}
V1.1.0:
#ifdef GD_ECLIPSE_GCC
/* retarget the C library printf function to the USART, in Eclipse GCC environment */
int __io_putchar(int ch)
{
    usart_data_transmit(EVAL_COM0, (uint8_t) ch );
    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
    return ch;
}
#else
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
    return ch;
}
#endif /* GD_ECLIPSE_GCC */

Fix file:
../Firmware/CMSIS/GD/GD32F527/Include/gd32f527.h
fix reason:
Add a firmware library version acquisition function to the firmware library. 
V1.0.0:
/* GD32F527 firmware library version number V1.0 */
#define __GD32F527_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version     */
#define __GD32F527_STDPERIPH_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version     */
#define __GD32F527_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version     */
#define __GD32F527_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]   release candidate */
#define __GD32F527_STDPERIPH_VERSION        ((__GD32F527_STDPERIPH_VERSION_MAIN << 24)\
                                             |(__GD32F527_STDPERIPH_VERSION_SUB1 << 16)\
                                             |(__GD32F527_STDPERIPH_VERSION_SUB2 << 8)\
                                             |(__GD32F527_STDPERIPH_VERSION_RC))
V1.1.0:
/* GD32F527 firmware library version number V1.0 */
#define __GD32F527_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version     */
#define __GD32F527_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version     */
#define __GD32F527_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version     */
#define __GD32F527_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
#define __GD32F527_STDPERIPH_VERSION        ((__GD32F527_STDPERIPH_VERSION_MAIN << 24)\
                                             |(__GD32F527_STDPERIPH_VERSION_SUB1 << 16)\
                                             |(__GD32F527_STDPERIPH_VERSION_SUB2 << 8)\
                                             |(__GD32F527_STDPERIPH_VERSION_RC))

Fix file:
../Firmware/CMSIS/GD/GD32F527/Include/system_gd32f527.h
fix reason:
Add a firmware library version acquisition function to the firmware library. 
V1.0.0:
none
V1.1.0:
/* firmware version can be aquired by uncommenting the macro */
#define __FIRMWARE_VERSION_DEFINE
#ifdef __FIRMWARE_VERSION_DEFINE
/* get firmware version */
extern uint32_t gd32f527_firmware_version_get(void);
#endif /* __FIRMWARE_VERSION_DEFINE */

Fix file:
../Firmware/CMSIS/GD/GD32F527/Source/system_gd32f527.c
fix reason:
Add a firmware library version acquisition function to the firmware library. 
V1.0.0:
none
V1.1.0:
#ifdef __FIRMWARE_VERSION_DEFINE
/*!
    \brief      get firmware version
    \param[in]  none
    \param[out] none
    \retval     firmware version
*/
uint32_t gd32f527_firmware_version_get(void)
{
    return __GD32F527_STDPERIPH_VERSION;
}
#endif /* __FIRMWARE_VERSION_DEFINE */

Fix file:
../Template/main.c
fix reason:
Display the firmware library version through USART in main function. 
V1.0.0:
none
V1.1.0:
#ifdef __FIRMWARE_VERSION_DEFINE
    uint32_t fw_ver = 0;
#endif

#ifdef __FIRMWARE_VERSION_DEFINE
    fw_ver = gd32f527_firmware_version_get();
    /* print firmware version */
    printf("\r\nGD32F527 series firmware version: V%d.%d.%d", (uint8_t)(fw_ver >> 24), (uint8_t)(fw_ver >> 16), (uint8_t)(fw_ver >> 8));
#endif /* __FIRMWARE_VERSION_DEFINE */
__________________________________________________________________________________________________________________________

______________________ENET________________________________________________________________________________________________ 
Fix file:
../Firmware/GD32F527_standard_peripheral/Source/gd32f527_enet.c
fix reason: 
Default to disabling carrier sensing to prevent half-duplex issues.
V1.0.0:
                | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \
V1.1.0:
                | ENET_CARRIERSENSE_DISABLE | ENET_RECEIVEOWN_ENABLE \					
__________________________________________________________________________________________________________________________

______________________TIMER_______________________________________________________________________________________________ 
Fix file:
../Firmware/GD32F527_standard_peripheral/Source/gd32f527_timer.c
fix reason: 
Fixed the bug of interfaces timer_flag_clear/timer_interrupt_flag_clear.
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
{
    TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
}

void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
{
    TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
}

V1.1.0:
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
{
    TIMER_INTF(timer_periph) = (~(uint32_t)flag);
}

void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
{
    TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
}
_________________________________________________________________________________________________________________________

______________________MISC_______________________________________________________________________________________________
Fix file:
../Firmware/GD32F527_standard_peripheral/Source/gd32f527_misc.c
fix reason: New function nvic_system_reset added.
V1.0.0:
none
V1.1.0:
/*!
    \brief      initiates a system reset request to reset the MCU
    \param[in]  none
    \param[out] none
    \retval     none
*/
void nvic_system_reset(void)
{
    NVIC_SystemReset();
}

../Firmware/GD32F527_standard_peripheral/Source/gd32f527_misc.h
fix reason: New function nvic_system_reset declaration added.
V1.0.0:
none
V1.1.0:
/* initiates a system reset request to reset the MCU */
void nvic_system_reset(void);
_________________________________________________________________________________________________________________________

______________________CAU_______________________________________________________________________________________________
Fix file:
../Firmware/GD32F527_standard_peripheral/Source/gd32f527_cau.c
fix reason: Fixed the bug of interface cau_flag_get.
V1.0.0:
#define FLAG_MASK            ((uint32_t)0x00000020U)

FlagStatus cau_flag_get(uint32_t flag)
{
    uint32_t reg = 0U;
    FlagStatus ret_flag = RESET;

    /* check if the flag is in CAU_STAT1 register */
    if(RESET != (flag & FLAG_MASK)) {
        reg = CAU_STAT1;
    } else {
        /* the flag is in CAU_STAT0 register */
        reg = CAU_STAT0;
    }

    /* check the status of the specified CAU flag */
    if(RESET != (reg & flag)) {
        ret_flag = SET;
    }

    return ret_flag;
}
V1.1.0:
FlagStatus cau_flag_get(uint32_t flag)
{
    uint32_t reg = 0U;
    FlagStatus ret_flag = RESET;

    /* check if the flag is in CAU_STAT1 register */
    if(1U == (flag >> 31U)) {
        reg = CAU_STAT1;
    } else {
        /* the flag is in CAU_STAT0 register */
        reg = CAU_STAT0;
    }

    /* check the status of the specified CAU flag */
    if(0U != (reg & flag)) {
        ret_flag = SET;
    }

    return ret_flag;
}

../Firmware/GD32F527_standard_peripheral/Source/gd32f527_cau.h
fix reason: New function nvic_system_reset declaration added.
V1.0.0:
#define CAU_FLAG_INFIFO             CAU_STAT1_ISTA                              /*!< IN FIFO flag status */
#define CAU_FLAG_OUTFIFO            CAU_STAT1_OSTA                              /*!< OUT FIFO flag status */
V1.1.0:
/* cau_stat1 register value */
#define CAU_FLAG_INFIFO             (CAU_STAT1_ISTA | BIT(31))                  /*!< IN FIFO flag status */
#define CAU_FLAG_OUTFIFO            (CAU_STAT1_OSTA | BIT(31))                  /*!< OUT FIFO flag status */
_________________________________________________________________________________________________________________________

______________________USB________________________________________________________________________________________________
Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Include\usb_iap_core.h
fix reason: 
Changing IAP commands due to IAP protocol modification
V1.0.0:
/* special commands with download request */
#define IAP_OPTION_BYTE1                    0x01U
#define IAP_ERASE                           0x02U
#define IAP_DNLOAD                          0x03U
#define IAP_LEAVE                           0x04U
#define IAP_GETBIN_ADDRESS                  0x05U
#define IAP_OPTION_BYTE2                    0x06U
V1.1.0:
/* special commands with download request */
#define IAP_READ_OPTION_BYTE                0x01U                                  /*!< read option byte request */
#define IAP_ERASE                           0x02U                                  /*!< erase request */
#define IAP_DOWNLOAD                        0x03U                                  /*!< download request */
#define IAP_LEAVE                           0x04U                                  /*!< leave request */
#define IAP_GETBIN_ADDRESS                  0x05U                                  /*!< get bin address request */
#define IAP_WRITE_OPTION_BYTE               0x06U                                  /*!< write option byte request */
#define IAP_UPLOAD                          0x07U                                  /*!< upload request */
#define IAP_CHECK_RDP                       0x08U                                  /*!< check rdp state request */

#define OPERATION_SUCCESS                   0x02U                                  /*!< operation success status */
#define OPERATION_FAIL                      0x5FU                                  /*!< operation fail status */
#define LEAVE_FINISH                        0x04U                                  /*!< leave finish status */
#define OB_WRITE_SUCCESS                    0x03U                                  /*!< OB write success status */
#define IS_RDP_MODE                         0xBBU                                  /*!< MCU RDP status */
#define IS_NORMAL_MODE                      0xA5U                                  /*!< MCU normal status */

#define IAP_HOST_ID                         0x01U                                  /*!< IAP host ID */
#define IAP_DEVICE_ID                       0x02U                                  /*!< IAP device ID */


Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP DATA OUT function due to IAP protocol modification
V1.0.0:
/*!
    \brief      handle data out stage
    \param[in]  udev: pointer to USB device instance
    \param[in]  ep_num: endpoint identifier
    \param[out] none
    \retval     none
*/
static uint8_t iap_data_out (usb_dev *udev ,uint8_t ep_num)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    if (0x01U == iap->report_buf[0]) {
        switch (iap->report_buf[1]) {
        case IAP_DNLOAD:
            iap_req_dnload(udev);
            break;

        case IAP_ERASE:
            iap_req_erase(udev);
            break;

        case IAP_OPTION_BYTE1:
            iap_req_optionbyte(udev, 0x01U);
            break;

        case IAP_LEAVE:
            iap_req_leave(udev);
            break;

        case IAP_GETBIN_ADDRESS:
            iap_address_send(udev);
            break;

        case IAP_OPTION_BYTE2:
            iap_req_optionbyte(udev, 0x02U);
            break;

        default:
            break;
        }
    }

    usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET);

    return USBD_OK;
}
V1.1.0:
/*!
    \brief      handle data OUT stage
    \param[in]  udev: pointer to USB device instance
    \param[in]  ep_num: endpoint number
    \param[out] none
    \retval     USB device operation status
*/
static uint8_t iap_data_out(usb_dev *udev, uint8_t ep_num)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    if(IAP_HOST_ID == iap->report_buf[0]) {
        switch(iap->report_buf[1]) {
        case IAP_DOWNLOAD:
            iap_req_download(udev);
            break;

        case IAP_ERASE:
            iap_req_erase(udev);
            break;

        case IAP_READ_OPTION_BYTE:
            iap_req_read_optionbyte(udev);
            break;

        case IAP_LEAVE:
            iap_req_leave(udev);
            break;

        case IAP_GETBIN_ADDRESS:
            iap_address_send(udev);
            break;

        case IAP_WRITE_OPTION_BYTE:
            iap_req_write_optionbyte(udev);
            break;

        case IAP_UPLOAD:
            iap_req_upload(udev);
            break;

        case IAP_CHECK_RDP:
            iap_check_rdp(udev);
            break;

        default:
            break;
        }
    }

    usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET);

    return USBD_OK;
}

Fix file:
\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP download request function due to IAP protocol modification
V1.0.0:
/*!
    \brief      handle the IAP_DNLOAD request
    \param[in]  udev: pointer to usb device instance
    \param[out] none
    \retval     none
*/
static void iap_req_dnload(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    if (0U != iap->transfer_times) {
        if (1U == iap->transfer_times) {
            if (0U == iap->lps) {
                iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE);
            } else {
                iap_data_write(&iap->report_buf[2], iap->base_address, iap->file_length % TRANSFER_SIZE);
                iap->lps = 0U;
            }

            iap->dev_status[0] = 0x02U;
            iap->dev_status[1] = 0x02U;
            iap_report_send (udev, iap->dev_status, IAP_IN_PACKET);
        } else {
            iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE);

            iap->base_address += TRANSFER_SIZE;
        }

        iap->transfer_times--;
    }
}
V1.1.0:
/*!
    \brief      handle the IAP_DOWNLOAD request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_download(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    iap->dev_status[0] = IAP_DEVICE_ID;

    /* get the target address to download */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    /* program the target address */
    if(FMC_READY == iap_data_write(&iap->report_buf[6], iap->base_address, TRANSFER_SIZE)) {
        iap->dev_status[1] = OPERATION_SUCCESS;
    } else {
        iap->dev_status[1] = OPERATION_FAIL;
    }

    iap_report_send(udev, iap->dev_status, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Adding IAP write option byte request function due to IAP protocol modification
V1.0.0:
none
V1.1.0:
/*!
    \brief      handle the IAP_WRITE_OPTION_BYTE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_write_optionbyte(usb_dev *udev)
{
    uint32_t option_byte_addr = 0U;
    uint16_t option_byte_size = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get option byte address address */
    option_byte_addr  = iap->report_buf[2];
    option_byte_addr |= (uint32_t)iap->report_buf[3] << 8;
    option_byte_addr |= (uint32_t)iap->report_buf[4] << 16;
    option_byte_addr |= (uint32_t)iap->report_buf[5] << 24;

    /* get option byte address size */
    if(OPT_BYTE_ADDR == option_byte_addr) {
        option_byte_size = OPT_BYTE_SIZE;
    }

    iap->dev_status[0] = IAP_DEVICE_ID;

    /* write option byte address data */
    if(FMC_READY == option_byte_write(option_byte_addr, &iap->report_buf[6], option_byte_size)) {
        iap->dev_status[1] = OB_WRITE_SUCCESS;
    } else {
        iap->dev_status[1] = OPERATION_FAIL;
    }

    iap_report_send(udev, iap->dev_status, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP erase flash request function due to IAP protocol modification
V1.0.0:
/*!
    \brief      handle the IAP_ERASE request
    \param[in]  udev: pointer to usb device instance
    \param[out] none
    \retval     none
*/
static void iap_req_erase(usb_dev *udev)
{
    uint32_t addr = 0U;

    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to erase */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= iap->report_buf[3] << 8U;
    iap->base_address |= iap->report_buf[4] << 16U;
    iap->base_address |= iap->report_buf[5] << 24U;

    /* get file length */
    iap->file_length = iap->report_buf[7];
    iap->file_length |= iap->report_buf[8] << 8U;
    iap->file_length |= iap->report_buf[9] << 16U;
    iap->file_length |= iap->report_buf[10] << 24U;

    iap->lps = iap->file_length % TRANSFER_SIZE;
    if (0U == iap->lps) {
        iap->transfer_times = iap->file_length / TRANSFER_SIZE;
    } else {
        iap->transfer_times = iap->file_length / TRANSFER_SIZE + 1U;
    }

    /* check if the address is in protected area */
    if (IS_PROTECTED_AREA(iap->base_address)) {
        return;
    }

    addr = iap->base_address;

    /* unlock the flash program erase controller */
    fmc_unlock();

    flash_erase(addr, iap->file_length, iap->report_buf);

    fmc_lock();

    iap->dev_status[0] = 0x02U;
    iap->dev_status[1] = 0x01U;

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);
}
V1.1.0:
/*!
    \brief      handle the IAP_ERASE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_erase(usb_dev *udev)
{
    uint32_t addr = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to erase */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    /* get file length */
    iap->file_length = iap->report_buf[6];
    iap->file_length |= (uint32_t)iap->report_buf[7] << 8;
    iap->file_length |= (uint32_t)iap->report_buf[8] << 16;
    iap->file_length |= (uint32_t)iap->report_buf[9] << 24;

    /* check if the address is in protected area */
    if(IS_PROTECTED_AREA(iap->base_address)) {
        return;
    }

    addr = iap->base_address;
    iap->dev_status[0] = IAP_DEVICE_ID;

    if(FMC_READY == flash_erase(addr, iap->file_length)) {
        iap->dev_status[1] = OPERATION_SUCCESS;
    } else {
        iap->dev_status[1] = OPERATION_FAIL;
    }

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP read option byte request function due to IAP protocol modification
V1.0.0:
/*!
    \brief      handle the IAP_OPTION_BYTE request
    \param[in]  udev: pointer to USB device instance
    \param[in]  option_num: number of option byte
    \param[out] none
    \retval     none
*/
static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num)
{
    uint8_t i = 0U;
    uint32_t address = 0U;

    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    iap->option_byte[0] = 0x02U;

    if (0x01U == option_num) {
        address = OPT_BYTE_ADDR1;
#ifdef OPT_BYTE_ADDR2
    } else if (0x02U == option_num) {
        address = OPT_BYTE_ADDR2;
#endif
    } else {
        return;
    }

    for (i = 1U; i < 17U; i++) {
        iap->option_byte[i] = *(uint8_t *)address;
        address++;
    }

    iap_report_send (udev, iap->option_byte, IAP_IN_PACKET);
}
V1.1.0:
/*!
    \brief      handle the IAP_READ_OPTION_BYTE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_read_optionbyte(usb_dev *udev)
{
    uint8_t i = 0U;
    uint32_t option_size = 0U, temp = 0U, option_address = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* read option address address */
    option_address = iap->report_buf[2] + (iap->report_buf[3] << 8) + (iap->report_buf[4] << 16) + (iap->report_buf[5] << 24);

    iap->option_byte[0] = IAP_DEVICE_ID;

    if(OPT_BYTE_ADDR == option_address) {
        option_size = OPT_BYTE_SIZE;
    }

    /* read option address content */
    for(i = 0U; i < (option_size / 4U); i++) {
        temp =  *(uint32_t *)option_address;
        iap->option_byte[4 * i + 5] = temp >> 24;
        iap->option_byte[4 * i + 4] = temp >> 16;
        iap->option_byte[4 * i + 3] = temp >> 8;
        iap->option_byte[4 * i + 2] = temp;
        option_address = option_address + 4U;
    }
    iap->option_byte[1] = OPERATION_SUCCESS;

    iap_report_send(udev, iap->option_byte, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing leave IAP mode request function due to IAP protocol modification
V1.0.0:
/*!
    \brief      handle the IAP_LEAVE request
    \param[in]  udev: pointer to usb device instance
    \param[out] none
    \retval     none
*/
static void iap_req_leave(usb_dev *udev)
{
    /* lock the internal flash */
    fmc_lock();

    /* generate system reset to allow jumping to the user code */
    NVIC_SystemReset();
}
V1.1.0:
/*!
    \brief      handle the IAP_LEAVE request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_leave(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to jump */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    iap->dev_status[0] = IAP_DEVICE_ID;
    iap->dev_status[1] = LEAVE_FINISH;

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);

    usbd_disconnect(udev);

    /* reset register */
    register_reset();

    /* jump to target */
    jump_to_execute(iap->base_address);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Changing IAP upload request function due to IAP protocol modification
V1.0.0:
none
V1.1.0:
/*!
    \brief      handle the IAP_UPLOAD request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_req_upload(usb_dev *udev)
{
    uint16_t packet_valid_length = 0U, i= 0U;
    uint32_t bin_flash_addr = APP_LOADED_ADDR;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    iap->bin_addr[0] = IAP_DEVICE_ID;

    /* get target flash address */
    bin_flash_addr  = iap->report_buf[2];
    bin_flash_addr |= (uint32_t)iap->report_buf[3] << 8;
    bin_flash_addr |= (uint32_t)iap->report_buf[4] << 16;
    bin_flash_addr |= (uint32_t)iap->report_buf[5] << 24;

    /* get current packet valid length */
    packet_valid_length = iap->report_buf[6];
    packet_valid_length |= iap->report_buf[7] << 8;

    /* get target flash address content */
    for(i = 0U; i < packet_valid_length; i++) {
        iap->bin_addr[i + 1] = REG8(bin_flash_addr + i);
    }

    iap_report_send(udev, iap->bin_addr, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\iap\Source\usb_iap_core.c
fix reason: 
Adding IAP check read protected request function due to IAP protocol modification
V1.0.0:
none
V1.1.0:
/*!
    \brief      handle the IAP_CHECK_RDP request
    \param[in]  udev: pointer to USB device instance
    \param[out] none
    \retval     none
*/
static void iap_check_rdp(usb_dev *udev)
{
    uint8_t mode = 0U;
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* check whether the SPC bit of FMC module is normal state */
    if(0xA5U != REG8(OPT_BYTE_ADDR)) {
        mode = IS_RDP_MODE;
    } else {
        mode = IS_NORMAL_MODE;
    }

    iap->bin_addr[0] = IAP_DEVICE_ID;
    iap->bin_addr[1] = mode;

    iap_report_send(udev, iap->bin_addr, IAP_IN_PACKET);
}

Fix file:
..\Firmware\GD32F527_usb_library\device\class\msc\Include\usbd_msc_scsi.h
fix reason: 
The statement here can be removed
V1.0.0:
extern const uint8_t msc_page00_inquiry_data[];
extern const uint8_t msc_mode_sense6_data[];
extern const uint8_t msc_mode_sense10_data[];
V1.1.0:
none

Fix file:
..\Firmware\GD32F527_usb_library\device\core\Source\usbd_core.c
fix reason: 
GD32F527 can not support USB high-speed core, it has only one full-speed core
V1.0.0:
void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core)
V1.1.0:
void usbd_init(usb_core_driver *udev, usb_desc *desc, usb_class_core *class_core)

Fix file:
..\Firmware\GD32F527_usb_library\device\core\Source\usbd_core.c
fix reason: 
The endpoint size in the endpoint descriptor is the lower 11 bits
V1.0.0:
uint16_t max_len = ep_desc->wMaxPacketSize;
V1.1.0:
uint16_t max_len = ep_desc->wMaxPacketSize & EP_MAX_PACKET_SIZE_MASK;

Fix file:
..\Firmware\GD32F527_usb_library\driver\Include\drv_usb_core.h
fix reason: 
Adding endpoint size mask
V1.0.0:
none
V1.1.0:
#define EP_MAX_PACKET_SIZE_MASK             0x07FFU                             /*!< endpoint maximum packet size mask */

Fix file:
..\Firmware\GD32F527_usb_library\driver\Include\drv_usb_regs.h
fix reason: 
Removing the core enumeration as GD32F527 has only one full-speed core
V1.0.0:
typedef enum
{
    USB_CORE_ENUM_HS = 0,                           /*!< USB core type is HS */
    USB_CORE_ENUM_FS = 1                            /*!< USB core type is FS */
} usb_core_enum;
V1.1.0:
none

Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usb_core.c
fix reason: 
GD32F527 can not support USB high-speed core, it has only one full-speed core
V1.0.0:
usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core)
V1.1.0:
usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs)

Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usb_core.c
fix reason: 
GD32F527 have no ULPI
V1.0.0:
#ifdef USBHS_EXTERNAL_VBUS_ENABLED
        /* use external VBUS driver */
        usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD;
#else
        /* use internal VBUS driver */
        usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD;
#endif /* USBHS_EXTERNAL_VBUS_ENABLED */
V1.1.0:
none

Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usb_host.c
fix reason: 
GD32F527 can not support USB high-speed
V1.0.0:
if (!pp->ep.dir) {
	if (PORT_SPEED_HIGH == pp->dev_speed) {
		pp_inten |= HCHINTEN_NYETIE;
		pp_inten |= HCHINTEN_ACKIE;
	}
}
V1.1.0:
none

Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usb_host.c
fix reason: 
As GD32F527 can not support USB high-speed, so it can not support PING protocol
V1.0.0:
/*!
    \brief      configure host pipe to do ping operation
    \param[in]  udev: pointer to USB device
    \param[in]  pipe_num: host pipe number which is in (0..7)
    \param[out] none
    \retval     operation status
*/
usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num)
{
    uint32_t pp_ctl = 0U;

    udev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U));

    pp_ctl = udev->regs.pr[pipe_num]->HCHCTL;

    pp_ctl |= HCHCTL_CEN;
    pp_ctl &= ~HCHCTL_CDIS;

    udev->regs.pr[pipe_num]->HCHCTL = pp_ctl;

    return USB_OK;
}
V1.1.0:
none


Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usbh_int.c
fix reason: 
The wakeup interrupt is repeated
V1.0.0:
if (intr & GINTF_WKUPIF) {
	/* clear interrupt */
	udev->regs.gr->GINTF = GINTF_WKUPIF;
}
V1.1.0:
none


Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usbh_int.c
fix reason: 
GD32F527 is embedded PHY by default
V1.0.0:
if (USB_EMBEDDED_PHY == udev->bp.phy_itf) {
V1.1.0:
none


Fix file:
..\Firmware\GD32F527_usb_library\driver\Source\drv_usbh_int.c
fix reason: 
As GD32F527 can not support USB high-speed, so it can not support PING protocol
V1.0.0:
if (URB_PING == pp->urb_state) {
	pp->err_count = 0U;
	usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF);
}
V1.1.0:
none


Fix file:
..\Firmware\GD32F527_usb_library\host\class\hid\Include\usbh_standard_hid.h
fix reason: 
The name of the structure has been changed since it is confusing
V1.0.0:
typedef struct _hid_mouse_info
{
    uint8_t x;
    uint8_t y;
    uint8_t buttons[3];
} hid_mouse_info;
V1.1.0:
typedef struct _mouse_report_data {
    uint8_t x;                                                                /*!< X coordinate value */
    uint8_t y;                                                                /*!< Y coordinate value */
    uint8_t buttons[3];                                                       /*!< button buff */
} mouse_report_data;


Fix file:
..\Firmware\GD32F527_usb_library\host\class\hid\Source\usbh_standard_hid.c
fix reason: 
It is changed as the structure has been changed
V1.0.0:
hid_mouse_info mouse_info;

uint8_t mouse_report_data[8] = {0U};

if(hid->len > sizeof(mouse_report_data)) {
	hid->len = sizeof(mouse_report_data);
}

hid->pdata = (uint8_t *)(void *)mouse_report_data;
V1.1.0:
mouse_report_data mouse_info;

uint8_t hid_mouse_info[8] = {0U};

if(hid->len > sizeof(hid_mouse_info)) {
	hid->len = sizeof(hid_mouse_info);
}

hid->pdata = (uint8_t *)(void *)hid_mouse_info;


Fix file:
..\Firmware\GD32F527_usb_library\host\core\Source\usbh_pipe.c
fix reason: 
As GD32F527 can not support USB high-speed, so it can not support PING protocol
V1.0.0:
if ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type)) {
	pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH);
}
V1.1.0:
none

Fix file:
..\Examples\USB\USB_Device\audio\inc\usb_conf.h
..\Examples\USB\USB_Device\cdc_acm\inc\usb_conf.h
..\Examples\USB\USB_Device\composite_dev_hid_printer\inc\usb_conf.h
..\Examples\USB\USB_Device\custom_hid\inc\usb_conf.h
..\Examples\USB\USB_Device\dev_firmware_update\inc\usb_conf.h
..\Examples\USB\USB_Device\in_application_program_hid\inc\usb_conf.h
..\Examples\USB\USB_Device\msc_cdrom\inc\usb_conf.h
..\Examples\USB\USB_Device\msc_udisk\inc\usb_conf.h
..\Examples\USB\USB_Device\standard_hid_keyboard\inc\usb_conf.h
..\Examples\USB\USB_Device\usb_printer\inc\usb_conf.h
..\Examples\USB\USB_Device\usb_host_hid_keyboard_mouse\inc\usb_conf.h
..\Examples\USB\USB_Device\usb_host_msc_udisk\inc\usb_conf.h
fix reason: 
GD32F527 can not support USB high-speed core, it has only one full-speed core
V1.0.0:
#ifdef USE_USB_FS
    #define USB_FS_CORE
#endif

#define __ALIGN_BEGIN
#define __ALIGN_END
V1.1.0:
none

Fix file:
..\Examples\USB\USB_Device\audio\inc\app.c
..\Examples\USB\USB_Device\cdc_acm\inc\app.c
..\Examples\USB\USB_Device\composite_dev_hid_printer\inc\app.c
..\Examples\USB\USB_Device\custom_hid\inc\app.c
..\Examples\USB\USB_Device\dev_firmware_update\inc\app.c
..\Examples\USB\USB_Device\in_application_program_hid\inc\app.c
..\Examples\USB\USB_Device\msc_cdrom\inc\app.c
..\Examples\USB\USB_Device\msc_udisk\inc\app.c
..\Examples\USB\USB_Device\standard_hid_keyboard\inc\app.c
..\Examples\USB\USB_Device\usb_printer\inc\app.c
fix reason: 
GD32F527 can not support USB high-speed core, it has only one full-speed core
V1.0.0:
usbd_init (&usbd_printer, USB_CORE_ENUM_FS, ...);
V1.1.0:
usbd_init(&usbd_printer, ...);


Fix file:
..\Examples\USB\USB_Device\in_application_program_hid\src\flash_operation.c
fix reason: 
Changing flash erase function due to IAP protocol modification
V1.0.0:
/*!
    \brief      erase flash
    \param[in]  address: erase start address
    \param[in]  file_length: file length
    \param[in]  report_buffer: report buffer
    \param[out] none
    \retval     MAL_OK if all operations are OK, MAL_FAIL else
*/
void flash_erase(uint32_t address, uint32_t file_length, uint8_t* report_buffer)
{
    uint16_t page_count = 0U, i = 0U;

    page_count = report_buffer[6];

    /* clear pending flags */
    fmc_flag_clear (FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);

    for (i = 0U; i < page_count; i ++) {
        /* call the standard flash erase-page function */
        fmc_page_erase(address);

        address += PAGE_SIZE;
    }
}
V1.1.0:
/*!
    \brief      erase flash
    \param[in]  address: erase start address
    \param[in]  file_length: file length
    \param[out] none
    \retval     state of FMC, refer to fmc_state_enum
*/
fmc_state_enum flash_erase(uint32_t address, uint32_t file_length)
{
    uint16_t page_count = 0U, i = 0U;
    fmc_state_enum fmc_state = FMC_READY;

    if(0U == (file_length % PAGE_SIZE)) {
        page_count = (uint16_t)(file_length / PAGE_SIZE);
    } else {
        page_count = (uint16_t)(file_length / PAGE_SIZE + 1U);
    }

    /* unlock the flash program erase controller */
    fmc_unlock();

    /* clear pending flags */
    fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);

    for(i = 0U; i < page_count; i ++) {
        /* call the standard flash erase-page function */
        fmc_state = fmc_page_erase(address);

        address += PAGE_SIZE;
    }

    /* lock the flash program erase controller */
    fmc_lock();

    return fmc_state;
}

Fix file:
..\Examples\USB\USB_Device\in_application_program_hid\src\flash_operation.c
fix reason: 
Changing flash write function due to IAP protocol modification
V1.0.0:
/*!
    \brief      write data to sectors of memory
    \param[in]  data: data to be written
    \param[in]  addr: sector address/code
    \param[in]  len: length of data to be written (in bytes)
    \param[out] none
    \retval     MAL_OK if all operations are OK, MAL_FAIL else
*/
void iap_data_write (uint8_t *data, uint32_t addr, uint32_t len)
{
    uint32_t idx = 0U;

    /* check if the address is in protected area */
    if (IS_PROTECTED_AREA(addr)) {
        return;
    }

    /* unlock the flash program erase controller */
    fmc_unlock();

    /* clear pending flags */
    fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);

    /* data received are word multiple */
    for (idx = 0U; idx < len; idx += 4) {
        if (FMC_READY == fmc_word_program(addr, *(uint32_t *)(data + idx))) {
            addr += 4U;
        } else {
            while(1){
            }
        }
    }

    fmc_lock();
}
V1.1.0:
/*!
    \brief      write data to sectors of memory
    \param[in]  data: data to be written
    \param[in]  addr: sector address/code
    \param[in]  len: length of data to be written (in bytes)
    \param[out] none
    \retval     MAL_OK if all operations are OK, MAL_FAIL else
*/
fmc_state_enum iap_data_write(uint8_t *data, uint32_t addr, uint32_t len)
{
    uint32_t idx = 0U;
    fmc_state_enum fmc_state = FMC_READY;

    /* check if the address is in protected area */
    if(IS_PROTECTED_AREA(addr)) {
        return FMC_BUSY;
    }

    /* unlock the flash program erase controller */
    fmc_unlock();

    /* clear pending flags */
    fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);

    /* data received are word multiple */
    for(idx = 0U; idx < len; idx += 4) {
        if(FMC_READY == fmc_word_program(addr, *(uint32_t *)(data + idx))) {
            addr += 4U;
        } else {
            while(1){
            }
        }
    }

    /* lock the flash program erase controller */
    fmc_lock();

    return fmc_state;
}

Fix file:
..\Examples\USB\USB_Device\in_application_program_hid\src\flash_operation.c
fix reason: 
Adding related operation due to IAP protocol modifications
V1.0.0:
none
V1.1.0:
fmc_state_enum option_byte_write(uint32_t mem_add, uint8_t *data, uint16_t len)

void jump_to_execute(uint32_t addr)

void register_reset(void)

static fmc_state_enum fmc_state_get(void)

static fmc_state_enum fmc_ready_wait(uint32_t timeout)


Fix file:
..\Examples\USB\USB_Device\standard_hid_keyboard\src\gd32f527_hw.c
fix reason: 
Repeated definition
V1.0.0:
#ifdef USE_USBFS
    #define USBFS_CORE
#endif /* USE_USBFS */

#ifdef USBFS_CORE
    #define RX_FIFO_FS_SIZE                         128
    #define TX0_FIFO_FS_SIZE                        64
    #define TX1_FIFO_FS_SIZE                        128
    #define TX2_FIFO_FS_SIZE                        0
    #define TX3_FIFO_FS_SIZE                        0

    #define USBFS_LOW_PWR_MGMT_SUPPORT
    #define USBFS_SOF_OUTPUT_ENABLED

#endif /* USBFS_CORE */
V1.1.0:
none

Fix file:
..\Examples\USB\USB_Host\usb_host_hid_keyboard_mouse\src\gd32f527_usb_hw.c
..\Examples\USB\USB_Host\usb_host_msc_udisk\src\gd32f527_usb_hw.c
fix reason: 
There is no relevant action about USB over current and SOF output in the code
V1.0.0:
#define HOST_OVRCURR_PORT                       GPIOE
#define HOST_OVRCURR_LINE                       GPIO_PIN_1
#define HOST_OVRCURR_PORT_SOURCE                GPIO_PORT_SOURCE_GPIOE
#define HOST_OVRCURR_PIN_SOURCE                 GPIO_PINSOURCE1
#define HOST_OVRCURR_PORT_RCC                   RCC_APB2PERIPH_GPIOE
#define HOST_OVRCURR_EXTI_LINE                  EXTI_LINE1
#define HOST_OVRCURR_IRQn                       EXTI1_IRQn

#define HOST_SOF_OUTPUT_RCC                     RCC_APB2PERIPH_GPIOA
#define HOST_SOF_PORT                           GPIOA
#define HOST_SOF_SIGNAL                         GPIO_PIN_8
V1.1.0:
none


Fix file:
..\Examples\USB\USB_Host\usb_host_hid_keyboard_mouse\src\gd32f527_usb_hw.c
..\Examples\USB\USB_Host\usb_host_msc_udisk\src\gd32f527_usb_hw.c
fix reason: 
Repeated operation
V1.0.0:
/*!
    \brief      configure USB GPIO
    \param[in]  none
    \param[out] none
    \retval     none
*/
void usb_gpio_config (void)
{
#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
    EXTI_InitPara EXTI_InitStructure;
#endif

#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT

    EXTI_ClearIntBitState(EXTI_LINE18);

    /* USB wakeup EXTI line configuration */
    EXTI_InitStructure.EXTI_LINE = EXTI_LINE18;
    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
    EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
    EXTI_InitStructure.EXTI_LINEEnable = ENABLE;
    EXTI_Init(&EXTI_InitStructure);

#endif
}
V1.1.0:
none


Fix file:
..\Examples\USB\USB_Host\usb_host_hid_keyboard_mouse\src\lcd_font.c
..\Examples\USB\USB_Host\usb_host_msc_udisk\src\lcd_font.c
fix reason: 
Chinese fonts compile with errors in some IDE
V1.0.0:
const typefont_GB162 hz16[] = {
    "鏄?,0x00,0x00,0x1F,0xF0,0x10,0x10,0x10,0x10,0x1F,0xF0,0x10,0x10,0x10,0x10,0x1F,0xF0,0x04,0x40,0x44,0x44,0x24,0x44,0x14,0x48,0x14,0x50,0x04,0x40,0xFF,0xFE,0x00,0x00,
    "绀?,0x00,0x00,0x3F,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x01,0x00,0x01,0x00,0x11,0x10,0x11,0x08,0x21,0x04,0x41,0x02,0x81,0x02,0x05,0x00,0x02,0x00,
    "娴?,0x00,0x04,0x27,0xC4,0x14,0x44,0x14,0x54,0x85,0x54,0x45,0x54,0x45,0x54,0x15,0x54,0x15,0x54,0x25,0x54,0xE5,0x54,0x21,0x04,0x22,0x84,0x22,0x44,0x24,0x14,0x08,0x08,
    "璇?,0x00,0x28,0x20,0x24,0x10,0x24,0x10,0x20,0x07,0xFE,0x00,0x20,0xF0,0x20,0x17,0xE0,0x11,0x20,0x11,0x10,0x11,0x10,0x15,0x10,0x19,0xCA,0x17,0x0A,0x02,0x06,0x00,0x02,
    0x00,
};

/* song typeface bold small 2 font */
const typefont_GB242 hz24[] = 
{
    "鏄?,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0x00,0x0F,0x03,0xC0,0x0C,0x00,0x40,0x1F,0xF8,0x60,0x18,0x00,0x60,0x08,0x00,0x40,0x0E,0x01,0xC0,0x07,0xFF,0x00,0x00,0x00,0x00,0x01,0x84,0x00,0x01,0x84,0x00,0x19,0x87,0x80,0x0F,0x8C,0xE0,0x07,0x8C,0x20,0x00,0xCC,0x00,0x03,0xFF,0xE0,0x1F,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    "绀?,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x1F,0xFF,0xC0,0x00,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xC0,0x3F,0xFF,0xE0,0x00,0x30,0x00,0x00,0x30,0x00,0x00,0x30,0x00,0x06,0x13,0x00,0x0C,0x13,0xC0,0x0C,0x18,0xF0,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    "娴?,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x39,0xFC,0x30,0x1F,0xCC,0x30,0x07,0x06,0xB0,0x0F,0x06,0xF0,0x19,0x07,0xB0,0x31,0x37,0xB0,0x31,0x36,0xF0,0x1F,0x27,0xF0,0x01,0x67,0xF0,0x01,0xE5,0xF0,0x01,0xE1,0xF0,0x00,0x41,0xF0,0x0C,0xF8,0xB0,0x3C,0xD8,0x30,0x00,0x8C,0x30,0x00,0x80,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    "璇?,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x03,0x60,0x0C,0x03,0x70,0x0C,0x03,0x30,0x00,0x3F,0xE0,0x00,0x3F,0x80,0x08,0x01,0x00,0x3C,0x01,0x80,0x04,0x7F,0x80,0x04,0x7D,0x80,0x0C,0x00,0x80,0x0C,0x10,0xC0,0x0C,0x10,0xC0,0x0C,0x18,0x40,0x0C,0x1C,0x60,0x0F,0x7E,0x60,0x06,0x70,0x30,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    0x00,
};
V1.1.0:
none
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